Abstract: The invention relates to a multiple-chamber container (1, 1*) for storing and mixing a multi-component liquid coating or adhesive system (M), comprising a first chamber (10) for a first mixing component (B) and at least one other chamber (20) for another mixing component (H), the first chamber (10) and the at least one other chamber (20) being separated by at least one separating wall (30) in liquid-tight fashion and the separating wall (30) comprising a pierceable separating layer (40). The multiple-chamber container further comprises at least one piercing element (50) for piercing the pierceable separating layer (40) in such a way that the first and the one other mixing component (B, H) mix in the first or the at least one other chamber (10, 20). The multiple-chamber container (1, 1*) is characterized in that the at least one other chamber (20) is coaxial to the first chamber (10), the separating layer (40) being partially formed in the separating wall (30).

Abstract: A photobioreactor is described for cultivating phototrophic organisms and in particular a mat, as can be used in one such photobioreactor. The mat has a plurality of first fibres which are light conductive along their longitudinal direction and are constructed to decouple light conducted in the longitudinal direction laterally, at least somewhat transversely to the longitudinal direction. The mat furthermore has a plurality of second fibres which are electrically conductive along their longitudinal direction. With the aid of one such mat, light can on the one hand be coupled in the interior of a photobioreactor. On the other hand, a travelling electric alternating field can be generated by applying a suitable polyphase voltage from a voltage source with the aid of electrically conductive second fibres. This alternating field can act on electrically charged particles.

Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.

Abstract: A memory controller is to interface with a memory, associated with a plurality of pins, based on a codeword. The codeword is to include a plurality of n-bit symbols. An n-bit symbol of the codeword is to be formed from a plurality of n bursts over time associated with one of the pins of the memory.

Abstract: A high performance computing system that includes a shared fabric memory and a plurality of processors is disclosed. A first processor is coupled to a local storage and executes a first process that, in combination with other processes, causes the plurality of processors to perform certain actions including transferring, from the shared fabric memory to the local storage, a first value corresponding to a first cell of a first set of cells and a first sweep of a stencil code. The actions further include transferring, from a first logical partition in the shared fabric memory associated with the first cell to the local storage, a second value corresponding to a second cell related to the first cell and not in the first set of cells. Further, these actions include updating, by the first process, the first value based on at least the first value and the second value.

Abstract: A high performance computing system that includes a shared fabric memory and a plurality of processors is disclosed. A first processor is coupled to a local storage and executes a first process that, in combination with other processes, causes the plurality of processors to perform certain actions including transferring, from the shared fabric memory to the local storage, a first value corresponding to a first cell of a first set of cells and a first sweep of a stencil code. The actions further include transferring, from a first logical partition in the shared fabric memory associated with the first cell to the local storage, a second value corresponding to a second cell related to the first cell and not in the first set of cells. Further, these actions include updating, by the first process, the first value based on at least the first value and the second value.

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Abstract: Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.

Abstract: A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.

Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.

Abstract: An elongated hollow optical waveguide (1) is described, as can be used in particular in a photobioreactor for supplying phototrophic organisms both with light and with nutrients. The optical waveguide (1) has a casing (3) made from transparent plastic, which surrounds a hollow core (5). The hollow core has a diameter of at least 1 mm, preferably at least 3 mm or at least 1 cm. A plurality of openings (7) with a diameter of at least 0.5 mm, preferably at least 1 mm, is constructed in the casing (3). Light can propagate through the transparent casing and preferably exit laterally (19) along the entire optical waveguide (1). Nutrients (15) can be conveyed through the hollow core (5) into the interior of the photobioreactor. Conversely, portions of the solution, to which organisms have been added, can also be sucked through the hollow core (5), for example in order to analyze the same.

Abstract: Write operations on main memory comprise predicting a last write in a dirty cache line. The predicted last write indicates a predicted pattern of the dirty cache line before the dirty cache line is evicted from a cache memory. Further, the predicted pattern is compared with a pattern of original data bits stored in the main memory for identifying changes to be made in the original data bits. Based on the comparison, an optimization operation to be performed on the original data bits is determined. The optimization operation modifies the original data bits based on the predicted pattern of a last write cache line before the last write cache line is evicted from the cache memory.

Abstract: A technique includes generating a checkpoint for an application that is executing on a plurality of nodes of a distributed computing system. Forming the checkpoint includes selectively regulating communication of data from the plurality of nodes to a storage subsystem based at least in part on a replication of the data among the nodes.

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.

Abstract: A photobioreactor is described for cultivating phototrophic organisms and in particular a mat, as can be used in one such photobioreactor. The mat has a plurality of first fibres which are light conductive along their longitudinal direction and are constructed to decouple light conducted in the longitudinal direction laterally, at least somewhat transversely to the longitudinal direction. The mat furthermore has a plurality of second fibres which are electrically conductive along their longitudinal direction. With the aid of one such mat, light can on the one hand be coupled in the interior of a photobioreactor. On the other hand, a travelling electric alternating field can be generated by applying a suitable polyphase voltage by means of a voltage source with the aid of electrically conductive second fibres. This alternating field can act on electrically charged particles.

Abstract: Examples of the present disclosure include methods, devices, and/or systems. Identifying network communication patterns can include analyzing a distributed computer program of a network, estimating virtual network communication traffic based on the analysis, and mapping the virtual network communication traffic to a physical network link. Identifying network communications patterns can also include identifying the network communication pattern and categorizing the physical communication network link based on an estimated communication intensity of the mapped communication traffic and the network communication pattern. Identifying network communication patterns can further include optimizing an energy used by the network based on the categorization.

Abstract: A memory device includes a group or block of k-level memory cells, where k>2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels.

Abstract: Write operations on main memory comprise predicting a last write in a dirty cache line. The predicted last write indicates a predicted pattern of the dirty cache line before the dirty cache line is evicted from a cache memory. Further, the predicted pattern is compared with a pattern of original data bits stored in the main memory for identifying changes to be made in the original data bits. Based on the comparison, an optimization operation to be performed on the original data bits is determined. The optimization operation modifies the original data bits based on the predicted pattern of a last write cache line before the last write cache line is evicted from the cache memory.