Abstract: A system for interference detection includes one or more processors are configured to receive from one or more access points within a wireless network information indicative of airtime usage of one or more client devices associated with the one or more access points, determine an amount of total interference for at least one of the access points on a first channel, the total interference including foreign interference and in-network interference, determine a correlation between the total interference and the airtime usage of the one or more client devices, determine an amount of the foreign interference or an amount of the in-network interference based on the correlation, and selectively switch the at least one of the access points from communicating on the first channel to communicating on a second channel based on the determined amount of the foreign interference or the determined amount of the in-network interference.

Abstract: A wireless system includes memory configured to store information of physical layer rates associated with power levels between a client device and respective access points. The power levels comprise information of amounts of power in signals received by the client device from the respective access points. The system includes one or more processors configured to: during a communication session between the client device and a first access point, determine a current power level between the client device and a second access point, access the information based on the current power level to determine an expected physical layer rate between the client device and the second access point, determine a current physical layer rate between the client device and the first access point, and determine whether to switch the communication session to the second access point based on the expected physical layer rate and the current physical layer rate.

Abstract: A shaped particle beam writing strategy can be used to write a pattern with a particle beam onto a substrate. The pattern comprises a circuit design that is fractured into a plurality of arbitrary polygons. The writing strategy comprises transforming and fracturing the arbitrary polygons into a plurality of restricted polygons, each restricted polygon being represented by a location coordinate, at least two dimension coordinates, and at least one external edge indicator. Thereafter, the restricted polygons are tiled into a set of tiles comprising interior tiles and external edge tiles. Flash data is assigned for each tile such that the interior tiles are assigned a first flash area and the external edge tiles are assigned a second flash area that is smaller than the first flash area. The flash data is arranged in a selected order to write the pattern with a modulated particle beam, such as an electron beam, on a substrate.