Abstract: A method of minimizing imprint in a ferroelectric capacitor uses a gradually attenuated AC field to electrically depolarize the ferroelectric capacitor before being packaged. The AC field is linearly attenuated, and generated using a series of voltage pulses, down to a minimum allowed voltage. A final pulse is a positive voltage to minimize hydrogen degradation during packaging. Thermal depoling can also be used.

Abstract: A method for improving data retention in a 2T/2C ferroelectric memory includes baking a ferroelectric memory configured to operate as an array of 1T/1C memory cells for a period of time, and then configuring the ferroelectric memory to function as an array of 2T/2C memory cells, wherein the baking pre-imprints the ferroelectric capacitors in the ferroelectric memory and stabilizes a 2T/2C opposite state margin and enhances data retention. A corresponding memory circuit for configuring an array of memory cells for either 1T/1C operation or 2T/2C operation includes a plurality of sense amplifiers, a configurable reference circuit coupled to a logic circuit, a memory array, and a column decoder, wherein components are coupled together through a bit line and a complementary bit line, and wherein the logic circuit can configure the reference circuit for 1T/1C operation or 2T/2C operation.

Abstract: A method for improving data retention in a 2T/2C ferroelectric memory includes baking a ferroelectric memory configured to operate as an array of 1T/1C memory cells for a period of time, and then configuring the ferroelectric memory to function as an array of 2T/2C memory cells, wherein the baking pre-imprints the ferroelectric capacitors in the ferroelectric memory and stabilizes a 2T/2C opposite state margin and enhances data retention. A corresponding memory circuit for configuring an array of memory cells for either 1T/1C operation or 2T/2C operation includes a plurality of sense amplifiers, a configurable reference circuit coupled to a logic circuit, a memory array, and a column decoder, wherein components are coupled together through a bit line and a complementary bit line, and wherein the logic circuit can configure the reference circuit for 1T/1C operation or 2T/2C operation.