Patents by Inventor Robert Starkston
Robert Starkston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923257Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.Type: GrantFiled: August 19, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
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Publication number: 20230130944Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: December 27, 2022Publication date: April 27, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Publication number: 20230040850Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Patent number: 11515248Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: September 1, 2020Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 11444033Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: GrantFiled: July 1, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
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Publication number: 20210384094Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.Type: ApplicationFiled: August 19, 2021Publication date: December 9, 2021Applicant: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
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Patent number: 11114353Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.Type: GrantFiled: March 30, 2016Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
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Publication number: 20210202441Abstract: Various embodiments are generally directed to an electronic assembly comprising at least two dies stacked on top of each other. Metal columns of different heights electrically connect the dies to a system substrate.Type: ApplicationFiled: February 5, 2016Publication date: July 1, 2021Applicant: INTEL CORPORATIONInventors: ENG HUAT GOH, CHU AUN LIM, UPENDRA R. SHETH, ROBERT STARKSTON
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Patent number: 11022792Abstract: Aspects of the embodiments are directed to coupling a permanent magnet (PM) with a microelectromechanical systems (MEMS) device. In embodiments, an adhesive, such as an epoxy or resin or other adhesive material, can be used to move the PM towards the MEMS device to magnetically couple the PM to the MEMS device. In embodiments, an adhesive that is configured to shrink up on curing can be applied (e.g., using a pick and place tool) to a location between the MEMS device and the PM. As a result of curing, the adhesive can pull the PM towards the MEMS device. In embodiments, an adhesive that is configured to expand as a result of curing can be applied to a location between the PM and a sidewall of the chassis. As a result of curing, the adhesive can push the PM towards the MEMS device. The adhesive can also secure the PM in place.Type: GrantFiled: December 27, 2016Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Kyle Yazzie, Anna M. Prakash, Suriyakala Ramalingam, Liwei Wang, Robert Starkston, Arnab Choudhury, Sandeep S. Iyer, Amanuel M. Abebaw, Nick Labanok
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Publication number: 20200395297Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 1, 2020Publication date: December 17, 2020Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Publication number: 20200335444Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Applicant: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
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Patent number: 10796988Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: June 7, 2018Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 10763215Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: GrantFiled: December 9, 2015Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
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Patent number: 10716214Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: GrantFiled: December 3, 2015Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Robert Starkston, Richard C. Stamey, Robert L. Sankman, Scott M. Mokler
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Publication number: 20190391386Abstract: Aspects of the embodiments are directed to coupling a permanent magnet (PM) with a microelectromechanical systems (MEMS) device. In embodiments, an adhesive, such as an epoxy or resin or other adhesive material, can be used to move the PM towards the MEMS device to magnetically couple the PM to the MEMS device. In embodiments, an adhesive that is configured to shrink up on curing can be applied (e.g., using a pick and place tool) to a location between the MEMS device and the PM. As a result of curing, the adhesive can pull the PM towards the MEMS device. In embodiments, an adhesive that is configured to expand as a result of curing can be applied to a location between the PM and a sidewall of the chassis. As a result of curing, the adhesive can push the PM towards the MEMS device. The adhesive can also secure the PM in place.Type: ApplicationFiled: December 27, 2016Publication date: December 26, 2019Applicant: Intel CorporationInventors: Kyle Yazzie, Anna M. Prakash, Suriyakala Ramalingam, Liwei Wang, Robert Starkston, Arnab Choudhury, Sandeep S. Iyer, Amanuel M. Abebaw, Nick Labanok
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Patent number: 10366951Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: June 12, 2017Date of Patent: July 30, 2019Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
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Patent number: 10304769Abstract: Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a second side of the package substrate. Solder balls may be coupled with the second side of the package substrate and the second die such that the solder balls are approximately coplanar. Other embodiments may be described and/or claimed.Type: GrantFiled: August 27, 2015Date of Patent: May 28, 2019Assignee: INTEL CORPORATIONInventors: Robert L. Sankman, Allan A. Ovrom, III, Robert Starkston, Oren Arad
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Publication number: 20190057937Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.Type: ApplicationFiled: December 9, 2015Publication date: February 21, 2019Applicant: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard C. Stamey
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Publication number: 20190057915Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.Type: ApplicationFiled: March 30, 2016Publication date: February 21, 2019Applicant: Intel CorporationInventors: Robert Starkston, Robert L. Sankman, Scott M. Mokler, Richard Christopher Stamey, Amruthavalli Pallavi Alur
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Publication number: 20180350737Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: June 7, 2018Publication date: December 6, 2018Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan