Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

Abstract: System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.

Abstract: System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.

Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Abstract: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

Abstract: An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.

Abstract: A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high.

Abstract: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Abstract: Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

Abstract: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Abstract: A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.

Abstract: A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught.

Abstract: A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

Abstract: A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.

Abstract: A method of digital resampling converts a channel dependent rate to a fixed rate while correcting gain and phase mismatch between I and Q branches in the resampling process and adjusts the sampler phase for T-spaced equalization.

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.