Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

Abstract: An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.

Abstract: A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

Abstract: An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

Abstract: The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.

Abstract: A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.

Abstract: The electrostatic discharge protection circuit includes: at least two bipolar transistors Q1-Qn coupled in series; a top one Qn of the at least two bipolar transistors coupled to a protected node 10; a bottom one Q1 of the at least two bipolar transistors coupled to a common node 12; at least two resistors R1-Rn coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one R1 of the at least two resistors coupled between a base of the bottom one Q1 of the at least two bipolar transistors and the common node 12.