Abstract: A circuit for controlling a switching regulator is provided. The circuit includes a first input to receive a feedback signal from the switching regulator proportional to an output voltage of the switching regulator, a second input to receive a voltage reference signal, an output to be coupled to an input of the switching regulator, an error amplifier having a first input terminal coupled to the first input to receive the feedback signal, a second input terminal coupled to the second input to receive the voltage reference signal, and an output terminal coupled to the output, and a compensation network coupled between the second input and the output. The compensation network includes a series combination of a first capacitance and a first resistance coupled between the second input and a node, a second resistance coupled between the node and the output, and a second capacitance coupled to the node.

Abstract: A switching regulator that includes a high-side MOSFET, a low-side MOSFET, a high-side driver circuit, a low-side driver circuit, and a capacitive coupling circuit. An output of the high-side driver circuit is coupled to a gate of the high-side MOSFET to control the high-side MOSFET to be substantially depleted during a first operational phase and to be substantially enhanced during a second operational phase. An output of the low-side driver circuit is coupled to a gate of the low-side MOSFET to control the low-side MOSFET to be substantially enhanced during the first operational phase and to provide a regulated drain-to-source current during the second operational phase. The capacitive coupling circuit is coupled to an input of the high-side driver circuit and the gate of the low-side MOSFET and decreases the regulated drain-to-source current during a transition from the first operational phase to the second operational phase.

Abstract: A circuit for controlling a switching regulator is provided. The circuit includes a first input to receive a feedback signal from the switching regulator proportional to an output voltage of the switching regulator, a second input to receive a voltage reference signal, an output to be coupled to an input of the switching regulator, an error amplifier having a first input terminal coupled to the first input to receive the feedback signal, a second input terminal coupled to the second input to receive the voltage reference signal, and an output terminal coupled to the output, and a compensation network coupled between the second input and the output. The compensation network includes a series combination of a first capacitance and a first resistance coupled between the second input and a node, a second resistance coupled between the node and the output, and a second capacitance coupled to the node.

Abstract: Systems and methods described herein provide for high speed power factor correction which can overcome or substantially alleviate the problems associated with changes in the operating conditions of a load or other transient events. The present technology senses the present state conditions of a signal to quickly and accurately determine the presence of an overtone component within the signal. The expected value of the overtone component is then determined based on the sensed state of the signal. Power factor correction is then performed to suppress the overtone utilizing a control signal formed based on the expected value of the overtone. By performing power factor correction based on the expected value, the present technology can provide high speed power factor correction which is not limited by the delay introduced by an adaptive feedback loop.

Abstract: A reverse current comparator for use in switching regulators includes a differential stage configured to encode the difference in voltage between an N and a P input. The differential stage feeds one or more gain stages. At least one of the gain stages includes one or more hysteresis devices. When the voltage of the N input exceeds the voltage of the P input by a predetermined margin, the hysteresis device causes the regulator to enter a triggered state in which it outputs a non-zero output voltage. Subsequent changes to the N and P inputs do not change the regulator output until a RESET input is asserted and which point the regulator enters a reset state and is ready to be triggered.

Abstract: Systems and methods described herein provide for high speed power factor correction which can overcome or substantially alleviate the problems associated with changes in the operating conditions of a load or other transient events. The present technology senses the present state conditions of a signal to quickly and accurately determine the presence of an overtone component within the signal. The expected value of the overtone component is then determined based on the sensed state of the signal. Power factor correction is then performed to suppress the overtone utilizing a control signal formed based on the expected value of the overtone. By performing power factor correction based on the expected value, the present technology can provide high speed power factor correction which is not limited by the delay introduced by an adaptive feedback loop.