Patents by Inventor Robert Swann
Robert Swann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934740Abstract: Methods, systems and apparatus for associating electronic devices together based on received audio commands are described. Methods for associating an audio-controlled device with a physically separate display screen device such that information responses can then be provided in both audio and graphic formats using the two devices in conjunction with each other are described. The audio-controlled device can receive audio commands that can be analyzed to determine the author, which can then be used to further streamline the association operation.Type: GrantFiled: August 9, 2019Date of Patent: March 19, 2024Assignee: Amazon Technologies, Inc.Inventors: Justin-Josef Angel, Eric Alan Breitbard, Sean Robert Ryan, Robert Steven Murdock, Michael Douglas McQueen, Ryan Charles Chase, Colin Neil Swann
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Patent number: 10132111Abstract: A bump stop assembly is provided for an access door. The assembly comprises a bump stop configured to couple to the access door or a door frame and a door closure gauge movably coupled to the bump stop. A closure pad couples the bump top to one of the door frame or the access door. The closure pad engages the other side of the access door and door frame when the door is closed. The thickness of a selected closure pad is determined based upon the extent that the door closure gauge protrudes relative to the bump stop.Type: GrantFiled: March 24, 2016Date of Patent: November 20, 2018Assignee: FORD GLOBAL TECHNOLOGIES, LLCInventors: Robert Swann, Brian Westgarth
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Publication number: 20160305174Abstract: A bump stop assembly is provided for an access door. The assembly comprises a bump stop configured to couple to the access door or a door frame and a door closure gauge movably coupled to the bump stop. A closure pad couples the bump top to one of the door frame or the access door. The closure pad engages the other side of the access door and door frame when the door is closed. The thickness of a selected closure pad is determined based upon the extent that the door closure gauge protrudes relative to the bump stop.Type: ApplicationFiled: March 24, 2016Publication date: October 20, 2016Inventors: Robert SWANN, Brian WESTGARTH
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Patent number: 8285975Abstract: A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.Type: GrantFiled: April 15, 2003Date of Patent: October 9, 2012Assignee: Broadcom Europe LimitedInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7818540Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.Type: GrantFiled: May 19, 2006Date of Patent: October 19, 2010Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20090100252Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.Type: ApplicationFiled: November 18, 2008Publication date: April 16, 2009Inventors: Stephen Barlow, Nell Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20080297657Abstract: The disclosed systems and methods achieve improved communication of the text in a video stream. Text may be processed separately from the video stream to suit the capabilities of a display device or to improve the availability of the textual information to users with special requirements. The disclosed methods and systems may be used, for example, in conjunction with set-top-box decoders, mobile telephones, and portable media players with small or low-resolution display screens.Type: ApplicationFiled: June 4, 2007Publication date: December 4, 2008Inventors: Richard Griffiths, Robert Swann, Neil Johnson, Kevin Bracey
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Publication number: 20080298769Abstract: The disclosed systems and methods achieve improved quality reverse playback of video though techniques for modifying the way in which video is encoded and stored. The methods and systems may be used, for example, in conjunction with a wide variety of media playing and recording devices, such as DVD recorders, set top boxes, personal video devices (PVR), and mobile phones. Any device that allows users to record video, either from a fixed source (e.g., set top box) or from life (e.g., mobile phone with built-in video camera, or a standard digital video camera), may use the disclosed methods and systems to give users a higher quality playback.Type: ApplicationFiled: June 4, 2007Publication date: December 4, 2008Inventors: Neil Johnson, Robert Swann, Richard Bruce Griffiths, Kevin Bracey
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Patent number: 7457941Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.Type: GrantFiled: January 3, 2006Date of Patent: November 25, 2008Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7350057Abstract: Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.Type: GrantFiled: November 6, 2006Date of Patent: March 25, 2008Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7203800Abstract: A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.Type: GrantFiled: December 1, 2005Date of Patent: April 10, 2007Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7200724Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grouType: GrantFiled: January 17, 2006Date of Patent: April 3, 2007Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20070061550Abstract: A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.Type: ApplicationFiled: November 6, 2006Publication date: March 15, 2007Inventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7167972Abstract: Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.Type: GrantFiled: October 31, 2002Date of Patent: January 23, 2007Assignee: Broadcom Europe LimitedInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7130985Abstract: Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.Type: GrantFiled: October 31, 2002Date of Patent: October 31, 2006Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20060224865Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.Type: ApplicationFiled: May 19, 2006Publication date: October 5, 2006Inventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Patent number: 7107429Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.Type: GrantFiled: March 1, 2006Date of Patent: September 12, 2006Assignee: Broadcom CorporationInventors: Stephen Barlow, Timothy Ramsdale, Robert Swann, Nel Bailey, David Plowman
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Patent number: 7080216Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grouType: GrantFiled: October 31, 2002Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20060155925Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grouType: ApplicationFiled: January 17, 2006Publication date: July 13, 2006Inventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
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Publication number: 20060146060Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.Type: ApplicationFiled: March 1, 2006Publication date: July 6, 2006Inventors: Stephen Barlow, Timothy Ramsdale, Robert Swann, Nel Bailey, David Plowman