Abstract: A peripheral device interrupt controller maintains a count of pending interrupt events for a peripheral device up to a preset limit and times a preset delay interval from a first pending interrupt event or last interrupt servicing before asserting an interrupt request. When the interrupt request is asserted, the then pending interrupt events can be serviced as a group by a central processing unit of a computer. The overhead of processing a separate interrupt request for each interrupt event is thus avoided. The preset limit and preset delay interval can be set under software control to control the rate at which interrupt requests can be asserted by the peripheral device.

Abstract: A system for configuring a network adapter of a computer without user intervention. Device information for the devices of the computer, including each network adapter, is collected to uniquely identify the devices and to describe the device characteristics associated with the operation of those devices with the computer. Computer resources, which support the functions of the devices within the computer, are allocated based upon this device information. This allocation process prevents a potential conflicting use of computer resources by the installed devices. A device driver, which enables communications between a corresponding device and the computer, is also identified and loaded for each of the devices in response to the allocation of computer resources. In response to loading the driver for each network adapter, each network configuration routine or layer for a particular interface of the corresponding network adapter is identified.

Abstract: A composite signal is formed by simultaneously transmitting multiple asynchronous data bit sequences, that are coded with respective spreading codes, in a single channel; and a circuit is provided which decodes any bit b(x) in that composite signal. This circuit includes a set of filters which are matched to all of the spreading codes and which obtain (a) a matched filter output signal y(x) for the x-th data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+k-1) for the k-1 data bits that immediately follow data bit b(x); K is the number of bit sequences in the composite signal. An arithmetic unit combines the matched filter output signals via the expression: ##EQU1## where H(x,x.+-.i) is the cross correlation of the spreading codes for data bits b(x) and b(x.+-.i) over the time period that those data bits overlap (and thus add) in the composite signal, and ESTb(x-i) is an estimate of data bit b(x-i) which precedes bit b(x).

Abstract: Data bits are decoded from a composite signal that is formed by coding multiple bit sequences with respective spreading codes, and transmitting the coded bit sequences simultaneously and asynchronously over a single channel in which the bit sequences are added. This decoding involves a metric in combination with a repetitive decision process which is only linearly dependent on the number of bit sequences in the composite signal.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of one of a set of microinstructions stored in a control store. The microinstructions have a data path control field, a condition/size field and a next address control field. A microinstruction logic control is responsive to the microinstructions, and a memory control unit that includes a data cache memory array operates asynchronously with respect to the data path unit, translating virtual memory addresses to access data from the data cache memory array or from the central memory unit.