Abstract: A technique facilitates collecting data, related to a fracturing, run-in-hole, or pull-out-of hole operation. A frac plug is provided with electronics for obtaining the desired information related to the operation. For example, the frac plug may be constructed with electronic sensors, a digital storage device, and a power supply or other power related equipment. Depending on the application, the frac plug may be a composite frac plug, degradable frac plug, dummy frac plug, or other suitable frac plug. Retrieval of the information obtained may be done via coupling with an associated device, e.g. inductive or physical coupling, by utilizing a broadcast transmitter/receiver, by physical retrieval of the storage device, or by physical retrieval of the dummy frac plug.

Abstract: An electrical assembly may include a bus bar assembly, a sensor assembly, including a circuit board connected to the bus bar assembly, and a sensor, a bracket connected to the bus bar assembly, and a cooling member connected to the bracket. A method of assembling an electrical assembly may include connecting a shunt resistor with a bus bar assembly, connecting a circuit board with the bus bar assembly, connecting the bus bar assembly with the bracket, disposing the cooling member on or about the bracket, and/or connecting the cooling member with the bracket.

Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.

Abstract: A non-volatile memory cell is disclosed with increased drive current. A low voltage read transistor is used to increase the drive current. However, with a low voltage read transistor, extra protection is needed to ensure the read transistor is not damaged by high voltage. In one aspect, an isolation transistor is inserted between the read transistor and a sense transistor. The isolation transistor, read transistor and sense transistor are connected in series. When a high voltage is used during an erase operation of the memory cell, the isolation transistor absorbs some of the voltage to protect the read transistor from an excessive voltage level.

Abstract: An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.