Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments of the present invention, the counts associated with the performance indicators may be checked to determine if the counts are above a threshold. If a count is above a threshold, the associated instruction/data address may be identified as a “hot spot” and optimization of the execution of the code may be performed based on the identification of the hot spot.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. there is a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.

Abstract: A method, apparatus and computer instructions for hardware assist for autonomically patching code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory.

Abstract: A method, apparatus, and computer instructions for counting interrupts by type. An interrupt count is incremented when a particular type of interrupt occurs. The count may be stored in the IDT or an interrupt count table outside the IDT. The interrupt unit increments the count each time a particular type of interrupt occurs. In the event of a potential count overflow, the mechanism of the present invention provides logic necessary to notify software in order to handle the overflow.

Abstract: A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring unit (PMU) is used to program hardware counters that collect events associated with a type of interrupt, including nested interrupts. The performance monitoring unit may also count events that occur while servicing interrupt requests based upon the state of interrupt processing. Events that are known to the performance monitoring unit such as instruction retired, TLB misses, may be counted at the same time using a number of performance monitoring counters in the performance monitoring unit.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, a compiler may obtain performance profile data, annotated by output obtained from the use of the performance indicators and counters, along with the instructions/data of the computer program and use this information to optimize the manner by which the computer program is executed, instructions/data are stored, and the like. The optimizations may be to optimize the instruction paths, optimize the time spent in initial application load, the manner by which the cache and memory is utilized, and the like.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments of the present invention, arithmetic combinations of counter values generated based on the encountering of performance indicators may be generated and compared to threshold values to determine whether to generate interrupts to the monitoring application. In such embodiments, the microcode of the processor is programmed to check the counter values of counters specified by the monitoring application, combine the counter values in a manner specified by the monitoring application, and then compare the combined value to a threshold value supplied by the performance monitoring application.

Abstract: A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch instructions that are executed in a processor to collect branch statistics. A set of branch statistics fields is allocated to associate with a branch instruction. When a program is executed, the stored statistics allows the program to look at the branch statistics in the counter to perform branch prediction. Hence, a user may use branch statistics values from the hardware counter to perform analysis on application code.

Abstract: A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.

Abstract: Performance events are counted for a computing system. This includes designating a first processor counter as a low-order counter for counting a certain performance event encountered by the processor and associating with the first counter a second counter as a high-order counter. The first counter is incremented responsive to detecting the performance event for a first processing thread. Responsive to a second thread, an accumulator in system memory for the first thread and first and second counters is updated. Responsive to the first thread becoming active, values of the first and second counters are loaded from the accumulator. Responsive to a user call to read and return a combined value, a first instance of the second counter is read, then the first counter is read and a second instance of the second counter is read before returning the combined value.

Abstract: A method and apparatus for providing an autonomic mechanism for tracking thread stacks during a trace of a computer program. The method and apparatus include hardware assistance mechanisms that allow the processor to autonomically maintain a work area for each thread where a call stack is stored. With the apparatus and method, the operating system of the computing device informs the operating system of the size of the data area to allocate to a particular thread work area. In addition, when a trace of a computer program is to be performed, the trace software, via the operating system, informs the processor to begin maintaining the thread call stack information in the thread work area. For each thread in the computer program execution, the processor maintains a work area having a size that is determined based on the size communicated by the operating system. The work area is designated by address and length information stored in control registers of the processor.

Abstract: A method, apparatus, and computer instructions for processing instructions. Responsive to receiving an instruction for execution in an instruction cache in a processor in the data processing system, a determination is made as to whether an indicator is associated with the instruction and whether the instruction is of a certain type within a range of instructions. An interrupt is generated if the indicator is associated with the instruction and the instruction is of the certain type within the range of instructions.

Abstract: A method, apparatus, and computer instructions for processing instructions. In response to receiving an instruction for execution in an instruction cache in a processor in the data processing system, a determination is made as to whether the instruction indicates enabling a mode of operation in which interrupts are to be generated. Responsive to receiving a subsequent instruction after receiving the instruction, a determination is made as to whether the instruction is of a certain type. If the mode of operation in which interrupts are to be enabled and the instruction is of the certain type, an interrupt is generated.

Abstract: A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, provides a coherent meaning relative to a previous value for the same thread, despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent means for updating performance counts.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically control an execution-path selection within the software application.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically improve the performance of the execution of an application by relocating code segments and data areas.

Abstract: A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are associated with instructions or memory locations, and processing of the performance indicators enables counting of events associated with execution of those instructions or events associated with accesses to those memory locations. The performance information that has been dynamically gathered from the assisting hardware is available to the software application during runtime in order to autonomically affect the behavior of the software application, particularly to enhance its performance. For example, the counted events may be used to autonomically collecting statistical information about the ability of a software application to successfully acquire a semaphore.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions. An instruction is received at a processor in the data processing system. If an indicator is associated with the instruction in which the indicator identifies a threshold value, execution of the instruction is counted if a time for executing the instruction exceeds the threshold value. Responsive to a request to access data, a determination is made as to whether the indicator is associated with the data. The indicator identifies a threshold value. Access to the data is counted if the indicator is associated with the data and if a time needed to access the data exceeds the threshold value.