Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the "flip" phase oldspace and newspace of each generation are exchanged. In the "trace" phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then "scavenged" to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a "cleaning oldspace" phase is performed as a low-priority background process to purge the entries for the virtual pages on which "obsolete" pointers reside.

Abstract: A ring network is comprised of slave devices (96) (98), (100) and (102) that are interconnected on a ring network. The slave device (96) is interfaced with a test/maintenance controller (120) through a serial transmission line (106). The slave device (96) is interfaced with the slave device (98) through a serial transmission line (108). The slave device (98) is interfaced with the slave device (100) through a line (110) and the slave device (102) is interfaced with the slave device (100) through a line (112) with the slave device (102) being interfaced with the controller (120) through a line (114). A clock is generated by the controller (120) and transmitted to each of the slave devices through a node (1188) to provide an asynchronous clock with respect thereto. Each of the slave devices has an internal synchronizing circuit (130) for synchronizing the internal operation of the devices with respect to the controller (120).