Abstract: Structures, materials and methods for resolving forward implantation skew in the transposed splitting of ion cut materials. By way of example a “material X” is described, such as in the form of a wafer or substrate, having a low resistivity device layer within which nanodevices can be fabricated, an insulation layer, a hydrogen getter layer (e.g., heavily doped region), and a diffusion layer. Devices fabricated in the device layer can be transferred by bonding the surface of the device layer to a target material and then injecting and diffusing hydrogen from the backside of material X through the diffusion layer to the hydrogen getter layer to form a weakened plane. A splitting process then separates the device layer from the remainder of the substrate. A method is also described for thermally isolating a device layer stack, or other target, from a heated diffusion layer when diffusing hydrogen to form the weakened plane.

Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms introduced into the solid material.

Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms introduced into the solid material.

Abstract: A method for the transposed splitting of ion cut materials. Acceptor centers are formed and selectively introduced into a solid material. In addition, atoms are introduced into the solid material at a location that is offset spatially from acceptor centers. The atoms introduced into the solid material are then transported to the location of the acceptor centers where they will then condense in the region of the acceptor centers. As a result, then any expunged layer that is formed by ion splitting as result of the atoms being introduced into the solid material will follow the contour of the location of the acceptor centers, and will thus be transposed from the initial location of the atoms ;introduced into the solid material.

Abstract: A process for direct bonding similar or dissimilar materials at low temperatures in which a material surface is rendered hydrophilic and reactive by creating nitrogen based radicals on the surface, the surface is direct bonded to a second surface, and the bonded surfaces are annealed at a temperature below approximately 500.degree. C. A nitrogen based constituent is combined with an activator to render the surface hydrophilic and reactive through ammonia plasma activation or activation by use of hydrofluoric acid.

Abstract: A micromachined pressure switch and method of fabrication from silicon wafers using aligned fusion bonding. Pattern etched thermally grown silicon dioxide insulating pads are used to determine the size of silicon pressure membranes on an upper silicon wafer, with the desired switch gap set by the oxide thickness. The silicon membranes are formed by controlled thinning the upper silicon wafers. V-shaped vent grooves are pattern etched into a bottom silicon wafer to form electrodes to which the insulating pads are fusion bonded. The area between the electrodes and the membrane forms wells of specified sizes into which the membranes deflect upon application of pressure. The pressure switch operates when the membrane is deflected to contact the electrodes in the bottom wafer, and closes at the desired pressure threshold for both directions of pressure change with negligible hysteresis. The method of fabrication applies to a single element pressure switch as well as to an array of pressure switches.

Abstract: A process for precision alignment and bonding of complementary micromechanical, electrical and optical structures. Surface features of the structures are critically aligned and brought into physical contact within atomic dimensions to form direct bonds without the use of adhesives. The bonds are initially formed at room temperature and then strengthened by a high temperature anneal. Three dimensional structures may be formed in separate prefabricated layers rather than monolithically through the use of this process.

Abstract: An improved integrated circuit structure is disclosed in which an active device is formed in contiguous portions of a single slot in an integrated circuit structure or substrate. The method of forming the single slot or merged slot device comprises forming a first portion of the slot, constructing at least a part of one element of the active device in this slot portion, and then forming one or more additional slot portions contiguous with the first slot portion, and constructing one or more further elements of the same active device in the additional contiguous slot portion or portions.

Abstract: An improved integrated circuit structure is disclosed which comprises a substrate having one or more active device slots with active elements of an active device formed therein and an isolation slot surrounding the one or more active device slots with an inner wall contiguous with the outer wall of the one or more active device slots. The active elements in the one or more active device slots are thereby in direct contact with isolation material in the isolation slot to thereby inhibit end effects.

Abstract: An improved bipolar slot transistor vertically formed in a slot in an integrated circuit structure is disclosed. The transistor is formed in a substantially vertical slot having an active base region formed beneath the bottom of the slot and comprises an active collector region formed beneath the active base region, a buried collector layer beneath the active collector region and in communication with a collector contact; an emitter region formed in the slot over the active base region; and extrinsic base regions formed adjacent to but insulated from the sidewalls of the slot communicating with the active base region and with base contact regions on the surface of the structure.

Abstract: A bipolar transistor susceptible to high level integration has its active regions formed in slots within a semiconductor substrate. In one embodiment, the emitter is formed within a slot and has a surrounding region doped to function as a base. A collector is formed in another slot which is located adjacent but spaced apart from the emitter slot. Carrier transport occurs principally horizontally between the emitter and base and then to the collector. Additional slots may be used to isolate the slot transistor in conjunction with a horizontally disposed pn junction and a buried collector. The collector may be formed in a slot which contains an oxidized outer sidewall that serves to isolate the individual transistor.

Abstract: Slots of different types are fabricated using a single latent image mask. The slots of different types are thus located with respect to each other in a self-aligned relationship. In one embodiment an oxide of the semiconductor material, e.g., silicon dioxide, is used as a unitary masking layer. The slots of various types are defined in the mask and are fabricated in succession by relying on a universal etch and differential thicknesses for the oxide layers over slots of the different types. When the slots are formed they are filled with a suitable material. In another embodiment at least a dual layer latent image mask is used in which the two materials have different etch properties. One layer is used as a stop etch layer during fabrication of one of the slot types.

Abstract: A slot formation process is provided in which the regions near the mouth of the slot are coated, while the slot is being formed, with a material which is resistant to the etchant being used to form the slot. The coating may be applied continuously or may be applied at specific points in the slot formation process. During the formation of the middle and bottom regions of the slot the coated upper regions retain a nearly vertical contour shape since they are protected from undesired etching by ions whose trajectories have been impacted by charge accumulations at the mouth of the slot. The coating material may be a thin oxide layer of the semiconductor material or may be a layer of an appropriate etch resistant material.

Abstract: In a charge coupled device provided with a two-phase overlapping gate structure, charge flow directionality is built into the structure by forming an asymmetrical potential well beneath each gate electrode with a single offset mask. High packing density is achieved in an array of staggered bits and with each bit being designed to have a geometry of minimum size.

Abstract: In a charge coupled device provided with a two-phase overlapping gate structure, charge flow directionality is built into the structure by forming an asymmetrical potential well beneath each gate electrode with a single offset mask. High packing density is achieved in an array of staggered bits and with each bit being designed to have a geometry of minimum size.

Abstract: A semiconductor substrate is coated with an insulating film followed by a layer of polysilicon. The polysilicon layer is coated with a non-oxidizable mask, such as silicon nitride, and then oxidized to convert the exposed regions to silicon oxide and add further thickness to the converted oxide regions. When the mask is removed, the thicker silicon oxide regions serve as an in situ mask for selectively implanting impurity ions through the thinner polysilicon regions and into the semiconductor substrate. When the silicon oxide regions are etched away, the remaining polysilicon regions serve as an ion implantation mask for permitting selective ion implantation through the voids left by etching the silicon oxide regions.