Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.

Abstract: A computing platform includes an array of interconnected field programmable gate arrays (FPGAs), memory, and external input/output interfaces. The platform is in the form of a blade conforming to the Advanced Telecommunications Computing Architecture (ATCA) standard. The platform is especially useful for telecommunications and networking applications.

Abstract: A computing platform includes an array of interconnected field programmable gate arrays (FPGAs), memory, and external input/output interfaces. The platform is in the form of a blade conforming to the Advanced Telecommunications Computing Architecture (ATCA) standard. The platform is especially useful for telecommunications and networking applications.

Abstract: A design environment for FPGA applications enables configuration of an FPGA platform to include a user design and one or more interface units, which the user design can use to access one or more external modules/devices without needing any particular knowledge of the structure and operation of such modules/devices. The interface unit corresponding to an external device/module, under the control of an operating environment, can establish a communication between the user design and the external module/device. An external processing module can use an interface unit to monitor and/or control a user design.

Abstract: A method and apparatus is disclosed herein for wireless communication with adaptive beamforming. In one embodiment, the apparatus comprises a processor, a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to and controlled by the processor to transmit content using adaptive beamforming, and an interface to a wireless communication channel coupled to the processor to communicate antenna information relating to the use of the phased array antenna and to communicate information to facilitate playing the content at another location.

Abstract: A transversal filter of the split electrode type employing a bucket-brigade device (BBD) is described. The BBD wells extend beyond the edges of the clocked gates of the BBD below second gates of different areas. These mask programmed second gates provide the filter output. Unlike other split electrode, capacitance sensing filters, these gates are not clocked, thus the filter has simplified output circuitry and a greater dynamic range.

Abstract: Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region.