Abstract: A controller includes first and second half bridge sense circuits coupled to a half bridge node. The half bridge node is coupled between a high side switch and a low side switch coupled to an input. A rising slew detection circuit is coupled to the first half bridge sense circuit to output a first slew detection signal in response to a rising slew event at the half bridge node. A falling slew detection circuit is coupled to the second half bridge sense circuit to output a second slew detection signal in response to a falling slew event at the half bridge node. A control circuit coupled to output a high side drive signal to the high side switch and a low side drive signal to the low side switch in response to the first slew detection signal, the second slew detection signal, and a feedback signal.

Abstract: A controller includes first and second half bridge sense circuits coupled to a half bridge node. The half bridge node is coupled between a high side switch and a low side switch coupled to an input. A rising slew detection circuit is coupled to the first half bridge sense circuit to output a first slew detection signal in response to a rising slew event at the half bridge node. A falling slew detection circuit is coupled to the second half bridge sense circuit to output a second slew detection signal in response to a falling slew event at the half bridge node. A control circuit coupled to output a high side drive signal to the high side switch and a low side drive signal to the low side switch in response to the first slew detection signal, the second slew detection signal, and a feedback signal.

Abstract: A field effect transistor (FET), according to the present invention, comprises a source and drain pair of electrodes having non-uniform charge distributions between them, such as results from small radius tips, and has a gate and channel structure that exists only between points of the source and drain pair that have the less intense charge distributions, e.g., areas not involving any small radius tips. The gate and channel structure is such that, given the non-uniform charge distributions between the source and drain pair of electrodes, the electric field is reduced around the tip by eliminating the n-well junction near the source-drain fingertips.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.