Abstract: Disclosed is a thermal environment enclosure for a semiconductor test system, said enclosure comprising a housing having an exterior surface, an interior chamber and a window therethrough. The housing further comprised of a substantially rectangular top, a pair of substantially rectangular side walls, a front wall, a back wall, a top perimeter edge, and a bottom perimeter edge with an attached sealing gasket. The bottom perimeter edge defines an opening into the interior chamber which is configured for sealed mating with the recessed test area to define a imposed thermal environment test area. The top of the housing comprises a hingeably attached lid with a closing latch, the lid including an attached interior surface sealing gasket defining the interior chamber in combination with other walls when the lid is closed.