Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract: A printed circuit card having first and second major surfaces joined by four minor surfaces and having I/O pads on either or both the major surfaces and on at least one of the minor surfaces.The printed circuit card can be formed from a stack of insulating layers, one or more of which has a pattern of conductive lines disposed thereon. Selected ones of these conductive lines terminate in respective I/O pads positioned on one of said major card surfaces. By providing separate additional I/O pads on one of the edges or minor surfaces of the card additional conductive lines can be placed on the cards and terminated.There is also disclosed a mating triplex connector socket for the improved card. This triplex connector comprises an elongated housing having a slot or recess therein for receiving the edge of the printed circuit card. Spring contacts are positioned along the walls and bottom of the recess for mating with and contacting the I/O pads positioned on the major and minor surfaces of the card.