Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: Digital signal delay lines with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times. Floating gate field effect transistors are programmed to select current, capacitance, and/or threshold and thereby set a delay time determined by acurrent charging of a capacitor up to a threshold voltage. Trimming after packaging avoids package offsets. Temperature and power supply voltage compensation by current combining gives compensation compatible with the electrical programming.

Abstract: An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff-frequency has its output connected to the clock input of a counter.

Abstract: An integrated circuit which uses an unusual comparator design, which is not fully complementary but which has an extended common mode range, to control switching of one pole of the output driver (e.g. the lower pole) between an internal voltage (e.g. ground voltage) and a current extracted from an incoming signal.

Abstract: An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff frequency has its output connected to the clock input of a counter.

Abstract: A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator.Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized.Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.

Abstract: A micropowered module containing an integrated circuit packaged with a battery. The module is originally in a state of zero power consumption. When the module is to be put into use, a very strong electromagnetic field is applied at a predetermined frequency. A preset pulse code at this frequency will activate logic elements to keep the integrated circuit turned on, in active or standby mode. In standby mode, the power from the battery will avoid data loss.