Abstract: A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits ?31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits ?2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match.