Patents by Inventor Robert Washburn
Robert Washburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872081Abstract: A relative navigation system projects a grid into space from a grid generator and an object, such as an unmanned aerial vehicle, may use the projected grid to aid in the landing of the object. Methods of adjusting the projected grid including stabilizing the projected grid and orienting the grid generator relative to the earth.Type: GrantFiled: November 1, 2011Date of Patent: October 28, 2014Assignee: GE Aviation Systems LLCInventors: Michael Steven Feldmann, Frank Saggio, III, John Robert Washburn
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Publication number: 20130107219Abstract: A relative navigation system projects a grid into space from a grid generator and an object, such as an unmanned aerial vehicle, may use the projected grid to aid in the landing of the object. Methods of adjusting the projected grid including stabilizing the projected grid and orienting the grid generator relative to the earth.Type: ApplicationFiled: November 1, 2011Publication date: May 2, 2013Applicant: GE AVIATION SYSTEMS LLCInventors: Michael Steven Feldmann, Frank Saggio, III, John Robert Washburn
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Flex Circuit Apparatus and Method for Adding Capacitance while Conserving Circuit Board Surface Area
Publication number: 20090300912Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.Type: ApplicationFiled: August 17, 2009Publication date: December 10, 2009Inventors: John Thomas, Russell Rapport, Robert Washburn -
Patent number: 7579971Abstract: The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.Type: GrantFiled: July 23, 2004Date of Patent: August 25, 2009Inventors: Robert Washburn, Robert F. McClanahan
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Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
Patent number: 7576995Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.Type: GrantFiled: November 4, 2005Date of Patent: August 18, 2009Assignee: Entorian Technologies, LPInventors: John Thomas, Russell Rapport, Robert Washburn -
Patent number: 7508723Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.Type: GrantFiled: May 24, 2007Date of Patent: March 24, 2009Assignee: Entorian Technologies, LPInventors: Paul Goodwin, Brian Miller, Robert Washburn
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Publication number: 20080291747Abstract: A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is configured to detect the low DQS state by comparing the low DQS state to a low voltage level of one of the plurality of drivers.Type: ApplicationFiled: May 24, 2007Publication date: November 27, 2008Applicant: STAKTEK GROUP L.P.Inventors: Paul Goodwin, Brian Miller, Robert Washburn
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Patent number: 7405634Abstract: An improved method and apparatus for altering the effective electrical length of trace on a circuit board. In the present invention small tabs of etch are routed perpendicular to the trace in the unused areas between adjacent traces. In an embodiment of the invention, a method of tuning the delay characteristics of a transmission line is implemented by inserting compensation tabs into the unused area between the segments of adjacent straight traces or a serpentine run. Utilizing the method and apparatus of the present invention, it is possible to achieve significantly greater electrical length for an electrical trace without introducing coupling problems or utilizing large amounts of space on a circuit board.Type: GrantFiled: January 30, 2004Date of Patent: July 29, 2008Assignee: Dell Products L.P.Inventors: James B. Mobley, Robert Washburn
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Publication number: 20070194813Abstract: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as a one-time part of the manufacturing process as determined by the requirements of the specific application. A digital-to-analog converter (DAC) circuit is used to input value selection data digitally, and control value selection with value resolution dependent on the resolution of the DAC. An alternate embodiment is provided for high frequency operation.Type: ApplicationFiled: November 7, 2006Publication date: August 23, 2007Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20070183228Abstract: The present system is an electronic circuit designed for incorporation on high-speed computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.Type: ApplicationFiled: October 26, 2006Publication date: August 9, 2007Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20070130760Abstract: A duct for containing a cable and method for mounting the cable therein include providing the duct with a collapsible or flexible wall movable between a contracted condition for mounting the duct in a conduit and an extended condition of increased cross-sectional area for inserting a cable in the duct. The duct is moved to its extended condition by an applied internal pressure and, after the cable has been inserted, the duct is returned to its contracted condition. The duct has a multiple layer construction: an inner layer, an outer protective layer and a reinforcing layer between them. There may be frictional reducing ribs on the inner and/or outer layer in order to reduce the forces necessary to place the duct and/or the cable. Alternatively, the duct may have a single, thin layer.Type: ApplicationFiled: February 26, 2007Publication date: June 14, 2007Applicant: ARNCO CORPORATIONInventor: Robert Washburn
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Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area
Publication number: 20070103877Abstract: An apparatus and a method for adding capacitance while conserving circuit board surface area. An apparatus for adding capacitance while conserving circuit board surface area includes a flex capacitor circuit with an upper surface and a lower surface and a plurality of conductive layers and an integrated-circuit (IC) device mounted on to the upper surface of the flex capacitor circuit and electrically connected to the flex capacitor circuit. The flex capacitor circuit is configured to provide bypass capacitance and, therefore, adds capacitance to the IC device when the IC device is mounted on the flex capacitor circuit.Type: ApplicationFiled: November 4, 2005Publication date: May 10, 2007Inventors: John Thomas, Russell Rapport, Robert Washburn -
Publication number: 20060294437Abstract: The invention is a point-of-load power conditioning system for computer memory modules that provides regulation and fast transient response for memory integrated circuit bias voltages. The invention uses low voltage drop regulation circuitry that is physically located on individual memory modules. Power consumption and memory module regulator power dissipation are minimized by use of off-module power preconditioning that provides module input power at an optimized voltage for the on-module regulator circuitry.Type: ApplicationFiled: June 22, 2006Publication date: December 28, 2006Applicant: Thunder Creative Technologies, Inc.Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20060285417Abstract: The invention is a clock interface circuit for high-speed computer memory modules. It provides improved timing margin due to improved rise and fall times than achieved with present JEDEC specified clock distribution and timing networks. The invention also provides for improved clock and inverse clock symmetry around VREF.Type: ApplicationFiled: May 24, 2006Publication date: December 21, 2006Applicant: THUNDER CREATIVE TECHNOLOGIES, INC.Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20060280004Abstract: The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.Type: ApplicationFiled: May 25, 2006Publication date: December 14, 2006Applicant: THUNDER CREATIVE TECHNOLOGIES, INC.Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20060044894Abstract: The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.Type: ApplicationFiled: August 17, 2005Publication date: March 2, 2006Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20050189980Abstract: The present invention is an electronic isolator that provides low input to output insertion loss, high output to input insertion loss, and substantial asymmetric isolation between a source circuit and a load circuit. The invention actively reduces noise and reflected power appearing on the isolator output. In numerous embodiments, the invention operates in circuit applications from dc through millimeter wave. Multistage electronic isolator embodiments provide increased isolation and greater noise reduction. In other embodiments, the electronic isolator also removes noise appearing on its input. In another embodiment, the invention is configured for high power applications. This embodiment includes circuitry for redirecting power away from the load into resistors or other dissipative elements. In another embodiment, the electronic isolator is configured to remove signal distortion produced by one or more power amplifiers in the system.Type: ApplicationFiled: April 21, 2005Publication date: September 1, 2005Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20050170691Abstract: An improved method and apparatus for altering the effective electrical length of trace on a circuit board. In the present invention small tabs of etch are routed perpendicular to the trace in the unused areas between adjacent traces. In an embodiment of the invention, a method of tuning the delay characteristics of a transmission line is implemented by inserting compensation tabs into the unused area between the segments of adjacent straight traces or a serpentine run. Utilizing the method and apparatus of the present invention, it is possible to achieve significantly greater electrical length for an electrical trace without introducing coupling problems or utilizing large amounts of space on a circuit board.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Inventors: James Mobley, Robert Washburn
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Publication number: 20050062631Abstract: The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.Type: ApplicationFiled: July 23, 2004Publication date: March 24, 2005Inventors: Robert Washburn, Robert McClanahan
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Publication number: 20050057276Abstract: The present invention provides termination for transmission line structures propagating common mode signals. Common mode signals typically represent noise in systems wherein information is transmitted as differential mode signals. The present invention terminates the common mode signals in a dynamically matched termination that prevents or significantly reduces reflection of said common signals without interference with differential mode transmission lines or their normal operation. Application is shown for an unshielded, twisted pair transmission line as commonly used in telephony-based systems for both voice and broadband data communication. The methods for application of the present invention to systems with large numbers of conductors are also shown.Type: ApplicationFiled: September 2, 2004Publication date: March 17, 2005Inventors: Robert Washburn, Robert McClanahan