Patents by Inventor Robert William Ryan

Robert William Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a heterojunction bipolar transistor
    Patent number: 6855613
    Abstract: A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: February 15, 2005
    Assignees: Lucent Technologies Inc., Agere Systems Inc.
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate, Yu-Chi Wang
  • Alignment techniques for epitaxial growth processes
    Patent number: 6294018
    Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: September 25, 2001
    Assignee: Lucent Technologies
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
  • Method for making InP heterostructure devices
    Patent number: 6165859
    Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: December 26, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
  • Trilayer lift-off process for semiconductor device metallization
    Patent number: 6156665
    Abstract: The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: December 5, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan
  • Method of manufacturing schottky gate transistor utilizing alignment techniques with multiple photoresist layers
    Patent number: 6139995
    Abstract: The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: October 31, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
  • Alignment techniques for photolithography utilizing multiple photoresist layers
    Patent number: 6042975
    Abstract: The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: March 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
  • Repairing fractured wafers in semiconductor manufacturing
    Patent number: 5932379
    Abstract: The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 3, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Jinwook Burm, Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate
  • INP heterostructure devices
    Patent number: 5907165
    Abstract: The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: May 25, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Robert William Ryan, Alaric Tate