Abstract: A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.

Abstract: A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.

Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.

Abstract: A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.

Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.

Abstract: Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×1016 cm?3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

Abstract: Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1×1016 cm?3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.