Patents by Inventor Robert Zucker

Robert Zucker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971463
    Abstract: Disclosed is a MTJ sensing circuit for measuring an external magnetic field and including a plurality of MTJ sensor elements connected in a bridge configuration, the MTJ sensing circuit having an input for inputting a bias voltage and generating an output voltage proportional to the external magnetic field multiplied by the bias voltage and a gain sensitivity of the MTJ sensing circuit, wherein the gain sensitivity and the output voltage vary with temperature; the MTJ sensing circuit further including a temperature compensation circuit configured to provide a modulated bias voltage that varies as a function of temperature over a temperature range, such that the output voltage is substantially constant as a function of temperature. Also disclosed is a method for compensating the output voltage for temperature.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 30, 2024
    Assignee: Allegro MicroSystems, LLC
    Inventors: Anuraag Mohan, Robert Zucker
  • Publication number: 20230134728
    Abstract: Magnetic sensor for measuring an external magnetic field angle in a two-dimensional plane, including: a first and second sensing unit outputting, respectively, a first signal sin(?) and a second signal cos(?); a first multiplying DAC receiving the first signal and a first digital input sin(f*t) and outputting a first modulated output signal; a second multiplying DAC receiving the second signal and a second digital input cos(f*t) and outputting a second modulated output signal; a first RC filter receiving the first modulated output signal and outputting a first filtered signal sin(?)*sin(f*t+RCd); a second RC filter receiving the second modulated output signal and outputting a second filtered signal sin(?)*sin(f*t+RCd); an adder adding the first and second filtered signals and outputting a summed signal cos(f*t+RCd+?); and an angle extracting unit for measuring the phase delay between the summed signal and a synchronization signal and determining the angle from the phase delay.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 4, 2023
    Inventors: Robert Zucker, Scott Fritz
  • Publication number: 20230119854
    Abstract: Disclosed is a MTJ sensing circuit for measuring an external magnetic field and including a plurality of MTJ sensor elements connected in a bridge configuration, the MTJ sensing circuit having an input for inputting a bias voltage and generating an output voltage proportional to the external magnetic field multiplied by the bias voltage and a gain sensitivity of the MTJ sensing circuit, wherein the gain sensitivity and the output voltage vary with temperature; the MTJ sensing circuit further including a temperature compensation circuit configured to provide a modulated bias voltage that varies as a function of temperature over a temperature range, such that the output voltage is substantially constant as a function of temperature. Also disclosed is a method for compensating the output voltage for temperature.
    Type: Application
    Filed: February 22, 2021
    Publication date: April 20, 2023
    Inventors: Anuraag Mohan, Robert Zucker
  • Publication number: 20070002174
    Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.
    Type: Application
    Filed: August 9, 2005
    Publication date: January 4, 2007
    Applicant: Intersil Americas Inc.
    Inventors: Zhinan Wei, Robert Zucker
  • Publication number: 20060061421
    Abstract: Ground skimming output stages that are designed to drive wideband signals with the ability to provide a high quality output signal all the way to the low supply rail are provided. In accordance with an embodiment of the present invention, the output stage of the present invention includes a translinear current controller, an output transistor and a current mirror. While not limited thereto, embodiments of the present invention only require a single positive power supply, consistent with the recent trend toward integrated circuits that only require a single low voltage power supply.
    Type: Application
    Filed: September 23, 2005
    Publication date: March 23, 2006
    Applicant: Intersil Americas Inc.
    Inventors: Robert Zucker, Barry Harvey
  • Patent number: 6556249
    Abstract: A method and apparatus for compensating for time base or phase errors in video and audio signals that are separately stored or processed. A ring oscillator provides a plurality of clock signals, each having a same frequency and slightly different phase. Each of the clock signals is applied to a multiplexor for allowing an appropriate one of the clock signals to be selected. By selecting appropriate ones of the clock signals in a sequence, the frequency and phase of an output clock signal formed by the multiplexor can be continuously and precisely controlled. Sync pulses separated from a video signal having a varying time base are applied to a video timing generator circuit which generates a series of digital values representative of timing differences between an expected occurrence of a sync pulse and an actual occurrence of the sync pulse. A phase accumulator accumulates the digital values over time for generating appropriate addresses for the multiplexor.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: April 29, 2003
    Assignee: Fairchild Semiconductors, Inc.
    Inventors: Gerard E. Taylor, Curtis Robinson, David W. Ritter, Robert Zucker
  • Patent number: 6107887
    Abstract: A two-stage differential to single-ended amplifier. The input stage converts a differential voltage to a differential current. A first pair of bipolar input transistors are biased with constant currents. Therefore, their on-resistance does not affect gain linearity. Changes in input voltages induce currents in a first pair of field effect transistors (FETs) each having a gate coupled to the collector of a corresponding input transistor and a drain coupled to the emitter of the corresponding input transistor. Differential currents are provided to the output stage by a second pair of FETs, each configured to mirror the current in a corresponding one of the first pair of FETs. Gain is adjustable by enabling additional pairs of FETs configured as current mirrors. The output stage includes a second pair of bipolar transistors with bases coupled together and biased with equal currents. Currents from the input stage are applied to the emitters of the second pair of bipolar transistors.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: August 22, 2000
    Assignee: Micro Linear Corporation
    Inventors: Robert Zucker, Carlos A. Laber, David Ritter