Abstract: A bit-error-rate detector (20) in a test set (10) for a frame-based communications channel employs a pseudo-random-number generator (46) at the channel's output end that generates a sequence the same as that produced by a pseudo-random-number generator (16) at the input end, but typically with a timing offset. A chain of delay circuits (38, 40, 42, and 44) receives the channel output. Each delay circuit imposes a delay equal to a single frame time and produces a respective output. One such output (CENTER) is normally compared in an XOR gate (52) with the output of the output-end pseudo-random-number generator (46). The XOR gate (52) applies signals indicative of any symbol mismatches to a shift register (88), which forwards them, after a delay, to a bit-error-rate counter (90).