Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.

Abstract: In accordance with an embodiment, an envelope detector includes a first transistor having a first current conduction terminal coupled to a first connection node; a second current conduction terminal coupled to an intermediate node; and a control terminal coupled the signal input node and to a biasing node; a second transistor having a first current conduction terminal coupled to the intermediate node; a second current conduction terminal coupled to a second connection node; and a control terminal coupled to the biasing node; and a first temperature compensating transistor that is diode-connected and coupled between a compensation output node and the biasing node. The second connection node is coupled to the compensation output node and the first connection node is coupled to a detector output.

Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.

Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.