Patents by Inventor Roberto Ganzelmi

Roberto Ganzelmi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6373288
    Abstract: A method is for implementing at least one clock tree in a synchronous digital electronic circuit. The method may include selecting an interchangeable programmable delay buffer stage, calculating an expected skew based upon the selected interchangeable programmable delay buffer stage, and interchanging the selected interchangeable programmable delay buffer stage with another if the expected skew is different from a desired skew. A related synchronous digital electronic circuit includes a plurality of clock trees, and an interchangable programmable delay buffer stage connected to each of the clock trees.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Ganzelmi, Cesare Pozzi, Alberto Battaia
  • Patent number: 6230308
    Abstract: The method relates to assembling modules for an integrated circuit comprising at least a plurality of modules. The method provides for the formation of at least one module architecture which comprises a plurality of modules and is aligned along one dimension of such modules. The invention also concerns an integrated circuit and a stacked module architecture obtained with the inventive assembling method.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: May 8, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Roberto Ganzelmi, Cesare Pozzi, Alberto Battaia
  • Patent number: 6166593
    Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: December 26, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Roberto Ganzelmi, Raffaele Costa, Cesare Pozzi
  • Patent number: 5774646
    Abstract: A method whereby the N elements of a memory are read sequentially, and the data items contained therein are compared with reference data items. Simultaneously with the reading of each element of the memory, its address is written in a number of redundancy check registers, each connected to a respective redundancy element. In the event the element of the memory differs from the reference data item, the first of the redundancy check registers is blocked to prevent it from being overwritten and the address of a faulty element of the memory is permanently stored. Upon the entire memory being read, the addresses of any faulty elements in the memory are thus already stored in the redundancy check registers.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: June 30, 1998
    Assignee: SGS Thomson Microelectronics S.r.l.
    Inventors: Saverio Pezzini, Roberto Ganzelmi, Maurizio Peri