Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.