Abstract: A multiplicity of peripheral units are consecutively scanned, in respective phases of a recurrent operating cycle, by a central unit including a processor for incoming and outgoing data. The processor is connected to a programmer emitting a series of binary instructions during each phase, the instructions being stored in a read-only memory from which they are read out during respective subphases of each phase under the control of an address counter, the last instruction of a series carrying a characteristic bit which advances a phase counter and causes a switch of the central unit to a different peripheral unit.