Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.

Abstract: The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells.

Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by:

Abstract: A semiconductor device comprising a non-volatile memory cell (20; 200) for storing a bit, arranged in a semiconductor substrate (21) containing a first dopant type, the memory cell including a drain (24) in the substrate (21), a floating gate (29), a control gate (30), a thin gate isolation layer (27), and an insulating layer (32), the insulating layer (32) being above the floating gate (29), the control gate (30) being above the insulating layer (32), the floating gate (29) being above the thin gate isolation layer (27), and the cell further including an access transistor (34) for controlling access to the non-volatile memory cell (20; 200), the cell (20; 200) including a buried substrate layer (22) containing a second dopant type and a source (26), and the access transistor (34) being formed in the substrate (21), in a trench adjacent to the floating gate (29), said trench extending substantially from the source (26) to the substrate's surface.

Abstract: A memory cell including: (a) a semiconductor substrate (1) provided with first and second diffusion layers (8); (b) a floating gate (11) on a floating gate insulating film (9); (c) a selection gate (4) on a selection gate insulating film (2); (d) a control gate (13) on a control gate insulating film (12); (e) the first and second diffusion layers (8) being arranged as the source and the drain of a field effect transistor structure, and the floating gate (11), selection gate (4) and control gate (13) being arranged as series field effect gates in the field effect transistor structure.

Abstract: A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR) a read transistor (TRE), a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi_p, Vsi_e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).

Abstract: A semiconductor device comprising a non-volatile memory cell (20; 200) for storing a bit, arranged in a semiconductor substrate (21) containing a first dopant type, said memory cell including a drain (24) in the substrate (21), a floating gate (29), a control gate (30), a thin gate isolation layer (27), and an insulating layer (32), the insulating layer (32) being above the floating gate (29), the control gate (30) being above the insulating layer (32), the floating gate (29) being above the thin gate isolation layer (27), and the cell further including an access transistor (34) for controlling access to the non-volatile memory cell (20; 200), the cell (20; 200) including a buried substrate layer (22) containing a second dopant type and a source (26), and the access transistor (34) being formed in the substrate (21), in a trench adjacent to the floating gate (29), said trench extending substantially from the source (26) to the substrate's surface.

Abstract: A semiconductor device comprising an EEPROM and a FLASH-EPROM memory is described. The EEPROM memory comprises a matrix of memory cells (ME) with a selection transistor (T2) having a selection gate (3) and arranged in series with a memory transistor (T1) having a floating gate (1) and a control gate (2). The selection transistor is also connected to a bit line (BL) and the memory transistor is also connected to a common source line (SO) of the EEPROM memory. The FLASH-EPROM memory comprises a matrix of memory cells (MF) with a memory transistor (T3) having a floating gate (4) and a control gate (5). The memory cells of the FLASH-EPROM memory also comprise a transistor (T4) having a control gate (6) connected in series with the memory cell. The memory transistor is also connected to a bit line, and the transistor, which is connected in series with the memory transistor, is also connected to a common source line (SO) of the FLASH-EPROM memory.

Abstract: A memory cell including: