Abstract: An efficient, gridless, cost-based coarse router having layer assignment for a computer controlled integrated circuit design. The coarse routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the coarse wire routing process, a number of obstructions are defined. Next, the horizontal and vertical passages between adjacent obstructions, through which wires may be routed, are determined. The costs for possible wire paths connecting a pair of pins are computed based upon wire density histograms associated with the various passages through which the paths traverse. The lowest cost path is then selected. In order to increase the processing speed, a pruning method is employed to minimize the number of possible paths to be considered. In some instances, there may be areas which are overly congested. For overly congested areas, a pseudo obstruction is artificially created by the coarse router.

Abstract: An efficient iterative, gridless, cost-based router for a computer controlled integrated circuit design. The fine routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the wire routing process, wires are routed between pins of nets. The routing process of the present invention is gridless and utilizes lanes that are defined based on the boundaries of objects. The cost-based router computes a cost for each wire path, and the cost is based on: (1) the manhattan wire distance: (2) the layers in which the wire runs; and (3) any overlap the wire has with soft obstacles (e.g., other wires, etc.); and (4) an estimated cost to the target. Cost computation is reduced by considering only obstacles within the layer in which a lane is run. The number of paths determined for a wire route is reduced by pruning possible paths based on the placement of obstacles within the integrated circuit.