Abstract: Embodiments of the present invention provide a data storage and retrieval system operating on a host computer. The data storage and retrieval system comprises a sparing system configured to replace defective memory sections of a memory device with replacement memory sections of the memory device, and an error correction code system. The error correction code system is configured to encode data with an error correction code to store the data into the memory device and decode the encoded data with the error correction code to retrieve the data from the memory device.

Abstract: A method of storing defective data site information for a storage device according to a particular embodiment of the invention includes determining a first defective data site associated with the storage device, determining a second defective data site associated with the storage device, determining a spacing value that represents spacing between the first defective data site and the second defective data site, and storing the spacing value. Apparatus and method aspects according to other embodiments of the invention also are disclosed.

Abstract: A memory card comprising a first modular component that comprises a first host interface and a first host interface module and a device interface module configured to operate a device interface that is coupled to a storage device. The first host interface module is configured to call a function in the device interface module. The first modular component is replaceable with a second modular component that comprises a second host interface and a second host interface module, and the second host interface module is configured to call the function in the device interface module.

Abstract: A memory card comprising a first modular component that comprises a first interface and first conductors and a data mover that comprises second conductors coupled to the first conductors. The first modular component is replaceable with a second modular component that comprises a second interface that differs from the first interface and third conductors that are configured to couple to the second conductors.