Abstract: A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

Abstract: A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

Abstract: A method and system for polishing a plurality of workpieces is disclosed. The method and system comprises providing a polishing tool with multiple polishing heads; and providing a substrate tray that can hold the plurality of work pieces in a fixed position on a tray underneath the polishing heads. The system and method includes moving the tray within the polisher. Finally, the method and system includes configuring the multiple polishing heads with the appropriate pad/slurry combinations to polish the workpieces and to create a finished polished surface on the plurality of work pieces.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A process is described for planarizing an isolation structure in a substrate. The process includes depositing a pad protective material over an upper surface of the substrate, and selectively removing portions of the pad protective material to expose portions of the substrate and to form sidewalls in the pad protective material. A trench is formed in the exposed portions of the substrate, and a trench fill material is deposited in the trench and over the pad protective material. A trench protective material is deposited over the trench fill material and in contact with the sidewalls of the pad protective material, such that the pad protective material and portions of the trench protective material together form a continuous protective material layer. Portions of the trench protective material and the trench fill material are selectively removed down to the level of the upper surface of the pad protective material.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.