Abstract: An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment wherein the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data from the event memory where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Abstract: A manufacturing process for LSIs uses an event tester to avoid prototype hold. The LSI manufacturing method includes the steps of: designing an LSI under an EDA (electronic design automation) environment to produce design data of a designed LSI, performing logic simulation on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation, verifying simulation data files with use of the design data and the testbench by operating an event tester simulator, producing a prototype LSI through a fabrication provider by using the design data, and testing the prototype LSI by an event tester by using the test vector file and the simulation data files and feedbacking test results to the EDA environment or the fabrication provider.

Abstract: An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

Abstract: A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules for easily establishing different semiconductor test systems. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test head to accommodate the two or more tester modules having different performances, means provided on the test head for electrically connecting the tester modules and a device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus. One type of the performances of the tester module is high speed high timing accuracy while other type of performance is low speed low timing accuracy. Each event tester module includes a tester board which is configured as an event based tester.

Abstract: An event based test system can generate scan vectors for testing a semiconductor device of scan design without requiring a large amount of scan memory. The test system includes an event memory for storing timing data and event type data of each event where the timing data is expressed by N data bits for defining one test vector, an event generator for generating an event with use of the timing data and the event type data, and a mode change circuit provided between the event memory and the event generator for changing signal paths between a normal mode for generating the test vectors and a scan mode for generating the scan vectors. In the test system, each bit of the N data bits in the event memory defines 2N scan vectors which are provided to the event generator in a series fashion, thereby producing the 2N scan vectors at each access of the event memory.

Abstract: A semiconductor test system is disclosed which accepts pincards from multiple vendors, each pincard including a local non-volatile memory in which specific calibration data can be stored. Each pincard in the test system may be capable of performing different types of tests on the DUT. Non-volatile memory on the pincard is used to store pincard calibration data, and loadboard and socket related calibration data may also be stored locally in the non-volatile memory of each pincard for use in compensating for signal degradation. Calibration data related to pincard slots (i.e. slot-to-slot skew) may be stored in nonvolatile memory on a test system backplane and used to calibrate slot-to-slot skew of the pincard.

Abstract: A semiconductor test system for testing a semiconductor device under test (DUT) is able to store failure data in a data failure memory with small memory capacity. The semiconductor test system includes a pattern memory for storing pattern data therein to produce a test pattern to be supplied to the DUT, means for evaluating an output signal of the DUT and producing failure data when there is a fail therein, a data failure memory for storing the failure data, and compaction means for assigning a plurality of addresses of the pattern memory to a single address of the data failure memory in a first test operation so that failure data occurred for each group of addresses of the pattern memory is stored in a corresponding address of the data failure memory, and for executing a second test operation for only a group of addresses of the pattern memory in which the failure data is detected without an address compaction.

Abstract: An event based test system has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein. The test system has a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT.

Abstract: A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.

Abstract: An event based test system is configured to test an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event formed with an integer multiple of a reference clock period and a fraction of the reference clock period wherein the timing data represents a time difference between a current event and a reference point, an address sequencer for generating address data for accessing the event memory, a timing count and scaling logic for generating an event start signal, an event generation unit for generating each event based on the event start signal and data indicating the fraction of the reference clock period, and a host computer for controlling an overall operation of the event based test system.

Abstract: A method and apparatus for design validation of complex IC with use of a combination of an event tester and a field programmable gate array (FPGA) or an emulator board. The design validation method eliminates logic simulation which is a bottleneck in design validation today. Because of the elimination of slow simulation from the design validation flow, extensive design validation can be done before design is taped-out for manufacturing, and because extensive design validation become possible, it eliminates the need of a prototype before mass production.

Abstract: A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

Abstract: A method of testing an embedded analog core in an integrated circuit chip having a microprocessor core and a memory core. The method includes the steps of providing a test register in the integrated circuit chip between the microprocessor core and an analog core to be tested, testing the microprocessor core and the memory core, using an assembly language test program running on the microprocessor core to generate a test pattern by the microprocessor core, applying the test pattern to the analog core by the microprocessor core and evaluating the response of the analog core either by the microprocessor core or a test system provided outside of the integrated circuit chip.

Abstract: An event based test system for testing semiconductor devices under test (DUT). The event based test system is freely configured to a plurality of groups of sin units where each group is able to perform test operations independently from the other. The start and end timings of the test in each group are independently made by generating multiple end of test signals. The event based test system includes a plurality of pin units to be assigned to pins of the DUT, a signal generator for generating an end of test signal for indicating an end of current test which is generated for each pin unit independently from other pin units, and a system controller for controlling an overall operation in the event based test system by communicating with each pin unit. The end of test signal for each pin unit is selected by condition specified by the system controller and the selected end of test signal is provided to the system controller and to the other pin units.

Abstract: A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.

Abstract: A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

Abstract: A test circuit is capable of testing functions of a microprocessor without involving any performance penalty or substantial increase in area overhead.

Abstract: A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.

Abstract: A method and structure for testing embedded memories in an integrated circuit chip having a microprocessor core therein. The method includes the steps of testing the microprocessor core by applying a test pattern and evaluating the resultant output of the microprocessor core, and confirming an integrity of the microprocessor core prior to testing the embedded memory, applying an object code of assembly language test program to the microprocessor core from a source external to the integrated circuit chip, generating a memory test pattern by the microprocessor core based on the object code of the assembly language test program, and applying the memory test pattern to the embedded memory and evaluating the resultant response of the memory by comparing the response with the expected data by the microprocessor core.

Abstract: Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops.