Abstract: An all-digital phase-locked loop (PLL) for synchronizing an output clock signal with a reference clock signal. The PLL has a multiple-tap, digital delay chain in its forward path for delaying the output clock signal, which delay chain is controlled by a digital number stored by a counter in its feedback path. A phase detector in the feedback path provides LEAD and LAG signals, the status of which indicates whether the output clock signal leads or lags the reference signal. In response to the LEAD and LAG signals, a digital sequencer in the feedback path generates the digital number and stores it in the counter. The digital sequencer changes the digital number until the state of the LEAD and LAG signals reverses, and then returns the counter back to its state prior to LEAD and LAG reversal, for synchronism. The digital sequencer also causes a phase reversal of the output signal where the number of delay taps needed for synchronism is large.

Abstract: A data processing system has a plurality of subsystems or terminals, each containing an independent processor, the terminals linked by a star coupler. The system includes a star coupler to which all the terminals are connected over sending and receiving transmission lines. The function of the coupler is to take the signals received by the coupler, logically ORing all these received signals, and redriving the resulting signal to all processors via the receive side transmission line. To prevent one terminal or processor from tying up the coupler for an undue length of time, the coupler includes means for detecting a message length exceeding a predefined maximum, and determines this to be an overrun condition. When the overrun occurs, the channel from the offending terminal or processor is blocked by the coupler from reaching the logical ORing functional center of the coupler. In this way, the linking section of the star coupler remains as an operative link among the remainder of the processors.

Abstract: A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.