Patents by Inventor Rod C. Langley
Rod C. Langley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7375036Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.Type: GrantFiled: August 5, 2002Date of Patent: May 20, 2008Assignee: Micron Technology, IncInventor: Rod C. Langley
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Patent number: 6686295Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.Type: GrantFiled: August 14, 2002Date of Patent: February 3, 2004Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Publication number: 20020192973Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.Type: ApplicationFiled: August 14, 2002Publication date: December 19, 2002Inventor: Rod C. Langley
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Publication number: 20020185470Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.Type: ApplicationFiled: August 5, 2002Publication date: December 12, 2002Inventor: Rod C. Langley
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Patent number: 6461976Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.Type: GrantFiled: May 16, 2000Date of Patent: October 8, 2002Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Patent number: 6133156Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.Type: GrantFiled: August 11, 1997Date of Patent: October 17, 2000Assignee: Micron Technology, Inc,Inventor: Rod C. Langley
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Patent number: 5958801Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.Type: GrantFiled: February 20, 1996Date of Patent: September 28, 1999Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Patent number: 5960314Abstract: A semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner conductive node and an elevationally outer conductive node includes, a) providing an inner node location to which electrical connection is to be made; b) providing an electrically insulative layer outwardly over the inner node location; c) patterning and etching a contact opening through the insulative layer to the inner node location; d) substantially filling the contact opening with an electrically conductive material to provide a conductive plug within the contact opening to the inner node location, the conductive plug defining an outermost fang gap between the conductive plug and the electrically insulative layer, the fang gap having a first width; e) widening the fang gap to a second width which is greater than the first width by a timed RF plasma etch of the electrically conductive material; f) providing an outer metal layer over the conductive plug after the widening step, the mType: GrantFiled: September 18, 1998Date of Patent: September 28, 1999Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Timothy P. O'Brien, Rod C. Langley
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Patent number: 5817573Abstract: In one aspect, a semiconductor processing method for connecting a metal layer to a plug when there is a fang gap between the plug and a layer surrounding the plug includes: a) forming a conductive material within an opening in a surrounding layer; b) etching the conductive material with a first etch chemistry to form a fang gap between the conductive material and the surrounding layer, the fang gap having a first width; c) etching the conductive material with a second etch chemistry to widen the fang gap to a second width which is greater than the first width, the second etch chemistry being different from the first etch chemistry; and d) providing an outer metal layer over the conductive plug after widening the fang gap, the metal layer at least partially filling the widened fang gap.Type: GrantFiled: December 8, 1995Date of Patent: October 6, 1998Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Timothy P. O'Brien, Rod C. Langley
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Patent number: 5496773Abstract: A semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner conductive node and an elevationally outer conductive node includes, a) providing an inner node location to which electrical connection is to be made; b) providing an electrically insulative layer outwardly over the inner node location; c) patterning and etching a contact opening through the insulative layer to the inner node location; d) substantially filling the contact opening with an electrically conductive material to provide a conductive plug within the contact opening to the inner node location, the conductive plug defining an outermost fang gap between the conductive plug and the electrically insulative layer, the fang gap having a first width; e) widening the fang gap to a second width which is greater than the first width by a timed RF plasma etch of the electrically conductive material; f) providing an outer metal layer over the conductive plug after the widening step, the mType: GrantFiled: April 28, 1995Date of Patent: March 5, 1996Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Timothy P. O'Brien, Rod C. Langley
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Patent number: 5385629Abstract: There is a post etching test apparatus and method to be able to only test just a few die on the wafer. Uniquely, the remainder of the die on the wafer can be salvaged, if the test identifies proper tolerances for the etching process over the entire wafer surface. If the tests show negative, the etch process can be re calibrated and the wafer can be reprocessed and tested again. Salvage of the majority of the die on the wafer under test is possible by using a fine point resist removal plate. Specifically, oxygen is forced over certain die on the wafer to remove the resist mask by using a plate barrier with only a few holes in it. The holes are located a key positions around the wafer, and restrain the oxygen laminar flow to effect only the wafers directly below these holes.Type: GrantFiled: October 14, 1993Date of Patent: January 31, 1995Assignee: Micron Semiconductor, Inc.Inventors: Alan J. Lamberton, Rod C. Langley
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Patent number: 5380401Abstract: The process of the present invention comprises the addition of an adequate amount of argon gas in a dry etch system to clear bond pads of residual contaminants which form an undesired oxide coating on the bond pads. Carbon dioxide may be used as a carrier gas along with the argon gas. The process of the present invention preferably takes place in situ, following the silicon nitride pad etch in which fluorine-containing chemicals are used to form the bond pads.Type: GrantFiled: January 14, 1993Date of Patent: January 10, 1995Assignee: Micron Technology, Inc.Inventors: Curtis S. Jones, William J. Crane, Robin L. Gilchrist, Rod C. Langley
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Patent number: 5271799Abstract: A method to anisotropically etch an oxide/metalsilicide/polysilicon sandwich structure on a silicon wafer substrate in situ, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a metalsilicide/polysilicon etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.Type: GrantFiled: July 20, 1989Date of Patent: December 21, 1993Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Patent number: 5201993Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step that utilizes C.sub.2 F.sub.6, CF.sub.4, CHF.sub.3 and an inert carrier gas as the etching atmosphere. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.Type: GrantFiled: August 27, 1990Date of Patent: April 13, 1993Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Patent number: 5169487Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step, both of which are performed as plasma etch steps. The process allows a continuous etch to be applied without removing the wafer from the plasma reactor chamber. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.Type: GrantFiled: August 27, 1990Date of Patent: December 8, 1992Assignee: Micron Technology, Inc.Inventors: Rod C. Langley, William J. Crane
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Patent number: 5094900Abstract: A self-aligned, sloped contact, through BPSG and thick TEOS (at least 200 nm but preferably 300-500 nm or more). Sloping is achieved through exploitation of BPSG and TEOS etch characteristics, to independently form concave and convex sidewalls, respectively. Self-alignment is obtained through thick conformal TEOS, along a sidewall of an underlying structure such as a transistor gate, directing contact formation away from the structure. TEOS etch is timed, allowing simultaneous formation of contacts to substrate and gates without overetching gates.Type: GrantFiled: April 13, 1990Date of Patent: March 10, 1992Assignee: Micron Technology, Inc.Inventor: Rod C. Langley
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Patent number: 4939105Abstract: The present invention is a contact etch method which simultaneously smoothes a reflowed oxide profile so that separate phanarization photoresist coat and etch steps are unnecessary. This method is characterized in that it is fast, uses only one photoresist mask layer, etches contacts to poly and to substrate simultaneously, is done entirely with plasma etch technology in a single reactor, and builds up less polymer in the plasma reactor. The novel method eliminates a coat and an etch step, improving yield and reducing fabrication time. Lower polymer buildup means higher yields due to a cleaner process, and less downtime for reactor chamber cleaning.Type: GrantFiled: August 3, 1989Date of Patent: July 3, 1990Assignee: Micron Technology, Inc.Inventor: Rod C. Langley