Patents by Inventor Rodney D. Greenstreet
Rodney D. Greenstreet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9310832Abstract: Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.Type: GrantFiled: October 30, 2012Date of Patent: April 12, 2016Assignee: National Instruments CorporationInventors: Jason W. Frels, Rodney D. Greenstreet, Gabriel L. Narus, Mark R. Wetzel
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Patent number: 9160472Abstract: Devices and methods for synchronizing devices over a switched fabric. A master device maintains a global time, determines a mapping between the global time and a counter of a switch over a memory-mapped fabric, and sends the mapping to a slave device. A slave device maintains a local time, determines a first mapping between the local time and a counter of a switch, receives a second mapping between the counter and a global time of the master device, and synchronizes its local time to the global time based on the first and second mappings. The master and slave device may map their times to the counter by sending respective request packets to the switch and receiving respective completion packets including respective counter values from the switch. The master and slave device may determine respective time values corresponding to the respective counter values based on in-switch delays of the packets.Type: GrantFiled: September 7, 2012Date of Patent: October 13, 2015Assignee: National Instruments CorporationInventors: Sundeep Chandhoke, Rodney D. Greenstreet
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Publication number: 20150103849Abstract: System and methods for synchronizing real time networks. Systems may include a first device located on a first real time network that may include a functional unit, a port, and a plurality of output queues configured for segregation of network packets based on a mapping of one or more additional real time networks to respective output queues. For each of the one or more additional real time networks, synchronization packets may be generated based on a master clock. The packets may be usable by a network timekeeper of the additional real time network to synchronize the additional real time network to the master clock. The synchronization packets may be stored in a respective output queue based on the mapping and may be sent to the network timekeeper of the additional real time network via the port.Type: ApplicationFiled: October 10, 2014Publication date: April 16, 2015Inventors: Sundeep Chandhoke, Rodney D. Greenstreet, Brian Keith Odom
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Publication number: 20150103848Abstract: Systems and methods for synchronizing clocks across networks using a time-sensitive (TS) network interface controller (NIC). The TS NIC may include a functional unit, a port, a clock, a plurality of input/output queue pairs, and a time stamp unit (TSU). The functional unit may be configured to generate synchronization packets usable by an NTS network timekeeper of a respective NTS network to synchronize the NTS network to the master clock, including using the TSU to generate time stamps for the synchronization packets in accordance with the clock synchronized to the master clock and communicate with the respective NTS network via the port using the corresponding input/output queue pair, including sending the synchronization packets to the NTS network timekeeper of the respective NTS network.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: NATIONAL INSTRUMENTS CORPORATIONInventors: Sundeep Chandhoke, Rodney D. Greenstreet, Brian Keith Odom
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Patent number: 9003220Abstract: Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet.Type: GrantFiled: September 7, 2012Date of Patent: April 7, 2015Assignee: National Instruments CorporationInventors: Sundeep Chandhoke, Rodney D. Greenstreet
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Publication number: 20140122915Abstract: Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: NATIONAL INSTRUMENTS CORPORATIONInventors: Jason W. Frels, Rodney D. Greenstreet, Gabriel L. Narus, Mark R. Wetzel
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Publication number: 20140071982Abstract: Devices and methods for synchronizing devices over a switched fabric. A master device maintains a global time, determines a mapping between the global time and a counter of a switch over a memory-mapped fabric, and sends the mapping to a slave device. A slave device maintains a local time, determines a first mapping between the local time and a counter of a switch, receives a second mapping between the counter and a global time of the master device, and synchronizes its local time to the global time based on the first and second mappings. The master and slave device may map their times to the counter by sending respective request packets to the switch and receiving respective completion packets including respective counter values from the switch. The master and slave device may determine respective time values corresponding to the respective counter values based on in-switch delays of the packets.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Inventors: Sundeep Chandhoke, Rodney D. Greenstreet
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Publication number: 20140075235Abstract: Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Inventors: Sundeep Chandhoke, Rodney D. Greenstreet
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Publication number: 20140019794Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.Type: ApplicationFiled: July 29, 2013Publication date: January 16, 2014Applicant: National Instruments CorporationInventors: Sundeep Chandhoke, Lee E. Mohrmann, Adam C. Ullrich, Rodney D. Greenstreet
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Patent number: 8583957Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.Type: GrantFiled: July 27, 2010Date of Patent: November 12, 2013Assignee: National Instruments CorporationInventors: Sundeep Chandhoke, Lee E. Mohrmann, Adam C. Ullrich, Rodney D. Greenstreet
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Publication number: 20120030495Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.Type: ApplicationFiled: July 27, 2010Publication date: February 2, 2012Inventors: Sundeep Chandhoke, Lee E. Mohrmann, Adam C. Ullrich, Rodney D. Greenstreet