Abstract: This disclosure describes techniques for recognizing gestures performed by a user, including techniques for conserving power when performing finger or hand gesture recognition operations that involve processing electromyography (EMG) data. In one example, a wearable device capable of being worn by a user comprises: a motion detector configured to detect motion of the wearable device; a tissue movement sensor configured to collect tissue movement information associated with motion of muscles or tissues beneath the user's skin; and a gesture detection module.

Abstract: This disclosure describes techniques for recognizing gestures performed by a user, including techniques for conserving power when performing finger or hand gesture recognition operations that involve processing electromyography (EMG) data. In one example, a wearable device capable of being worn by a user comprises: a motion detector configured to detect motion of the wearable device; a tissue movement sensor configured to collect tissue movement information associated with motion of muscles or tissues beneath the user's skin; and a gesture detection module.

Abstract: This disclosure describes techniques for recognizing gestures performed by a user, including techniques for conserving power when performing finger or hand gesture recognition operations that involve processing electromyography (EMG) data. In one example, a wearable device capable of being worn by a user comprises: a motion detector configured to detect motion of the wearable device; a tissue movement sensor configured to collect tissue movement information associated with motion of muscles or tissues beneath the user's skin; and a gesture detection module.

Abstract: This disclosure describes techniques for recognizing gestures performed by a user, including techniques for conserving power when performing finger or hand gesture recognition operations that involve processing electromyography (EMG) data. In one example, a wearable device capable of being worn by a user comprises: a motion detector configured to detect motion of the wearable device; a tissue movement sensor configured to collect tissue movement information associated with motion of muscles or tissues beneath the user's skin; and a gesture detection module.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor also includes a cache memory, comprising an array of storage elements for storing cache lines, indexed by an index input. One of the storage elements of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer is storing a replacement candidate line for the prefetched cache line. The microprocessor also includes control logic that determines whether the replacement candidate line in the cache memory is invalid, and if so, replaces the replacement candidate line in the one of the storage elements with the prefetched cache line from the prefetch buffer.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system memory coupled to the microprocessor. The microprocessor includes a cache memory, comprising an array of storage elements for storing cache lines. The array is indexed by an index input. The microprocessor includes a counter that counts a number of accesses to a replacement candidate line in the cache. The replacement candidate line is stored in a storage element of the array indexed by an index portion of an address of the prefetched cache line stored in the prefetch buffer. The microprocessor also includes control logic that selectively replaces the replacement candidate cache line in the cache memory with the prefetched cache line from the prefetch buffer based on the number of accesses to the replacement candidate line.

Abstract: A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates an allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first cache line in an exclusive state and to copy the contents of a second cache line into the first cache line. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first cache line in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second cache line into the first cache line.

Abstract: A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines into the first block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first block of cache lines in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second block of cache lines into the first block of cache lines.

Abstract: A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state, where the extended prefetch instruction is encoded to direct the microprocessor to prefetch the cache line in the exclusive state. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state, where the cache line comprises a data entity that is to be subsequently modified, and where prefetching the cache line in the exclusive state occurs in parallel with execution of program instructions prior to execution of a subsequent store instruction that directs the microprocessor to modify the data entity.

Abstract: An apparatus for speculatively forwarding storehit data in a microprocessor pipeline. First and second virtual address comparators compare a virtual load address with first and second virtual store addresses to generate a virtual match signal for indicating whether first and second storehit data is likely present in a store buffer and a result forwarding cache, respectively. If the first and second storehit data are both present the second storehit data is newer than the first storehit data. First and second physical address comparators compare a physical load address translated from the virtual load address with first and second physical store addresses translated from the plurality of virtual store addresses to generate a physical match signal for indicating whether the first and second storehit data is certainly present in the store buffer and the result forwarding cache, respectively.

Abstract: A microprocessor prioritizing cache line fill requests according to request type rather than issuing the requests in program order is disclosed. The requests are generated within the microprocessor at a core clock frequency, which is a multiple of the clock frequency of a bus coupling the microprocessor to a system memory from which the requests are satisfied. The request types are a blocking type and one or more non-blocking types. Blocking requests are initially assigned a higher priority than non-blocking requests. Once per bus clock, the highest priority request is selected for issuance on the bus, and the priority of each of the non-selected requests is increased. If more than one request is highest priority, the highest priority requests are selected in round-robin order. A request may have its priority changed if an event occurs which affects its type.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.

Abstract: A microprocessor with an apparatus for alleviating the need to maintain coherency between cache line status of a store buffer and a response buffer each storing the same cache line address is disclosed. The store buffers include match bits. When a store operation requires a response buffer to be allocated (e.g., to receive a cache line implicated by a store miss of a write-allocate cache or to obtain exclusive ownership of a shared cache line hitting in the cache), control logic populates the match bits to specify which of the response buffers was allocated. Control logic updates the cache line status in the allocated response buffer as status-altering events occur, which is subsequently used to update the cache, thereby alleviating the need for the store buffer to maintain the cache line status. If the store address matches an already-allocated response buffer, that response buffer is specified in the match bits.

Abstract: An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.

Abstract: Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies the floating point format. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the associated floating point operation according to the floating point format specified by the extended prefix.

Abstract: An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.