Patents by Inventor Roger A. Dufresne
Roger A. Dufresne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230050049Abstract: The present invention relates to a novel water sports device that allows a user to perform water skiing and other activities while sitting on the device. The device includes a toboggan style structure positioned atop a pair of water skis. The pair of skis are secured to the underside of the toboggan using a plurality of panels or supports so that the skis partially overlap and extend beyond the edges of the toboggan. Each of the pair of skis comprise a binding which is sized and configured to accommodate a foot of the user while sitting on the toboggan. The device provides enhanced balance, buoyancy, and floating capability, and also comprises a backrest for supporting the back of the user while enjoying the device on the water.Type: ApplicationFiled: June 8, 2022Publication date: February 16, 2023Inventor: Roger Dufresne
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Patent number: 10103060Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.Type: GrantFiled: June 18, 2015Date of Patent: October 16, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: David G. Brochu, Jr., Roger A. Dufresne, Baozhen Li, Barry P. Linder, James H. Stathis, Ernest Y. Wu
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Patent number: 9851398Abstract: Various particular embodiments include a via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.Type: GrantFiled: March 30, 2015Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Fen Chen, Roger A. Dufresne, Charles W. Griffin, Kevin W. Kolvenbach
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Patent number: 9780031Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.Type: GrantFiled: September 4, 2014Date of Patent: October 3, 2017Assignee: GLOBALFOUDRIES INC.Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
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Publication number: 20160372389Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.Type: ApplicationFiled: June 18, 2015Publication date: December 22, 2016Inventors: David G. Brochu, JR., Roger A. Dufresne, Baozhen Li, Barry P. Linder, James H. Stathis, Ernest Y. Wu
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Publication number: 20160291084Abstract: Various particular embodiments include a via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Inventors: Fen Chen, Roger A. Dufresne, Charles W. Griffin, Kevin W. Kolvenbach
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Patent number: 9453873Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.Type: GrantFiled: January 14, 2014Date of Patent: September 27, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Fen Chen, Roger A. Dufresne, Kevin Kolvenbach, Michael A. Shinosky
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Publication number: 20160071790Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.Type: ApplicationFiled: September 4, 2014Publication date: March 10, 2016Inventors: Fen CHEN, Cathryn J. CHRISTIANSEN, Roger A. DUFRESNE, Charles W. GRIFFIN
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Publication number: 20150221567Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.Type: ApplicationFiled: April 17, 2015Publication date: August 6, 2015Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
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Publication number: 20150198654Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Fen Chen, Roger A. Dufresne, Kevin Kolvenbach, Michael A. Shinosky
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Patent number: 9059052Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.Type: GrantFiled: May 16, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
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Patent number: 9029172Abstract: An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.Type: GrantFiled: January 20, 2012Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: Fen Chen, Roger A. Dufresne, Timothy D. Sullivan, Yanfeng Wang
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Patent number: 8917104Abstract: A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.Type: GrantFiled: August 31, 2011Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Fen Chen, Roger A. Dufresne, Kai D. Feng, Richard J. St-Pierre
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Publication number: 20140339558Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.Type: ApplicationFiled: May 16, 2013Publication date: November 20, 2014Applicant: International Business Machines CorporationInventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
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Patent number: 8890556Abstract: An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.Type: GrantFiled: October 26, 2011Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Fen Chen, Roger A. Dufresne, Kai D. Feng, Richard J. St-Pierre
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Patent number: 8754655Abstract: Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.Type: GrantFiled: August 11, 2011Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: David G. Brochu, Jr., Fen Chen, Roger A. Dufresne, Travis S. Merrill, Michael A. Shinosky
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Publication number: 20130191047Abstract: An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen CHEN, Roger A. DUFRESNE, Timothy D. SULLIVAN, Yanfeng WANG
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Publication number: 20130106452Abstract: An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Roger A. Dufresne, Kai D. Feng, Richard J. St-Pierre
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Publication number: 20130049793Abstract: A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Roger A. Dufresne, Kai D. Feng, Richard J. St-Pierre
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Publication number: 20130038334Abstract: Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David G. Brochu, JR., Fen Chen, Roger A. Dufresne, Travis S. Merrill, Michael A. Shinosky