Patents by Inventor Roger Cheng

Roger Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133925
    Abstract: Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.
    Type: Application
    Filed: October 23, 2022
    Publication date: April 25, 2024
    Inventors: Chia How Low, Roger Cheng
  • Patent number: 11960480
    Abstract: Provided is a system that includes at least one processor programmed or configured to receive an XML data file, wherein the XML data file includes data associated with one or more input parameters of a machine learning model, generate a code generation template based on the data associated with one or more input parameters of the machine learning model included in the XML file, where the code generation template includes one or more keys associated with one or more parameters of a transaction aggregate for an account of a user, and generate a file of executable code based on the code generation template, wherein the file of executable code includes instructions that, when executed by at least one processor, causes at least one processor to retrieve transaction aggregate data associated with the transaction aggregate for the account of the user. A method and computer program product are also provided.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: April 16, 2024
    Assignee: Visa International Service Association
    Inventors: Hongqin Song, Yu Gu, Roger Cheng-Chung Huang, Ran Xu, Shawn Johnson
  • Publication number: 20240055042
    Abstract: An apparatus, system, and method for improved memory control are provided. A circuit can include controller circuitry configured to determine, based on a speed of silicon of a memory, a read strobe code that adjusts a data clock to account for a difference between a reference clock and a data clock in terms of a number of unit intervals (UIs) and a read strobe code, a receive delay locked loop to receive the difference and delay the data clock by the number of UI and read strobe codes resulting in a delayed data clock, and a sampling amplifier to sample data from the memory based on the delayed data clock.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Chia How Low, Roger Cheng, Aaron K. Martin
  • Patent number: 11722128
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Publication number: 20220335040
    Abstract: Provided is a system that includes at least one processor programmed or configured to receive an XML data file, wherein the XML data file includes data associated with one or more input parameters of a machine learning model, generate a code generation template based on the data associated with one or more input parameters of the machine learning model included in the XML file, where the code generation template includes one or more keys associated with one or more parameters of a transaction aggregate for an account of a user, and generate a file of executable code based on the code generation template, wherein the file of executable code includes instructions that, when executed by at least one processor, causes at least one processor to retrieve transaction aggregate data associated with the transaction aggregate for the account of the user. A method and computer program product are also provided.
    Type: Application
    Filed: September 5, 2019
    Publication date: October 20, 2022
    Inventors: Hongqin Song, Yu Gu, Roger Cheng-Chung Huang, Ran Xu, Shawn Johnson
  • Publication number: 20210320652
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Applicant: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Patent number: 11070200
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Publication number: 20200106430
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
  • Patent number: 9391813
    Abstract: A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 12, 2016
    Assignee: MaxLinear, Inc.
    Inventors: Rama Akella, Roger Cheng
  • Patent number: 8027395
    Abstract: A method for performing channel estimation of an OFDM channel includes, in part, interpolating pilots for sub-channels positioned within a first range of an OFDM symbol, and estimating frequency response of sub-channels positioned within a second range of the OFDM symbol. The first range is defined by subchannels positioned substantially away from channel edges and the second range is defined by subchannels positioned substantially near channel edges. The method optionally includes transforming the pilots from frequency domain into the time-domain, time-domain windowing to obtain a channel impulse response having a multitude of discrete values, estimating the discrete values within the channel impulse response; and transforming the channel impulse response to the frequency domain.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: September 27, 2011
    Assignee: MaxLinear, Inc.
    Inventors: Ramakrishna Akella, Roger Cheng
  • Patent number: 7929645
    Abstract: An efficient channel estimation system and method provides good performance under high Doppler conditions and is suitable for OFDM systems such as DVB-T. A number of different pilot interpolations techniques enable the estimation of channel for the OFDM systems. For 2k and 4k modes, the channel is estimated using the preceding symbol, the present symbol, and two succeeding symbols. For an 8k mode, only one future symbol is used to estimate the channel.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: April 19, 2011
    Assignee: MaxLinear, Inc.
    Inventors: Rama Akella, Roger Cheng
  • Patent number: 7523221
    Abstract: Described is a system and method for applying transforms to multi-part files. A request is received to access a stream within a multi-part file. Upon receipt of the request, a list of transforms associated with the stream is identified. The list is also included within the multi-part file. The transforms specified in the list of transforms are performed on data before completing the request. If the request is a write, the transforms encode the data. If the request is a read, the transforms decode the data. The list of transforms is order dependent. The list of transforms includes a data structure having a first stream that includes a map that correlates the stream with a name for the list of transforms. A second stream that lists each of the transforms for the stream. A third stream for each of the transforms listed that identifies information associated with the transform.
    Type: Grant
    Filed: May 17, 2003
    Date of Patent: April 21, 2009
    Assignee: Microsoft Corporation
    Inventors: Michael J. Hillberg, Roger Cheng, David B. Ornstein, Jason M. Cahill
  • Publication number: 20080198942
    Abstract: A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 21, 2008
    Applicant: MaxLinear, Inc.
    Inventors: Rama Akella, Roger Cheng
  • Publication number: 20080144730
    Abstract: A method for performing channel estimation of an OFDM channel includes, in part, interpolating pilots for sub-channels positioned within a first range of an OFDM symbol, and estimating frequency response of sub-channels positioned within a second range of the OFDM symbol. The first range is defined by subchannels positioned substantially away from channel edges and the second range is defined by subchannels positioned substantially near channel edges. The method optionally includes transforming the pilots from frequency domain into the time-domain, time-domain windowing to obtain a channel impulse response having a multitude of discrete values, estimating the discrete values within the channel impulse response; and transforming the channel impulse response to the frequency domain.
    Type: Application
    Filed: November 5, 2007
    Publication date: June 19, 2008
    Applicant: MaxLinear, Inc.
    Inventors: Ramakrishna Akella, Roger Cheng
  • Publication number: 20080112494
    Abstract: An efficient channel estimation system and method provides good performance under high Doppler conditions and is suitable for OFDM systems such as DVB-T. A number of different pilot interpolations techniques enable the estimation of channel for the OFDM systems. For 2k and 4k modes, the channel is estimated using the preceding symbol, the present symbol, and two succeeding symbols. For an 8k mode, only one future symbol is used to estimate the channel.
    Type: Application
    Filed: October 11, 2007
    Publication date: May 15, 2008
    Applicant: MaxLinear, Inc.
    Inventors: Rama Akella, Roger Cheng
  • Publication number: 20060245519
    Abstract: An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver calibration pulse generator generates an IR calibration pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Inventors: Roger Cheng, Harishankar Sridharan, Navneet Dour, Hing To
  • Publication number: 20060245473
    Abstract: An embodiment of the present invention is a technique to integrate data for a source synchronous protocol. A delay generator generates at least an integrating strobe from a data strobe synchronizing a data having a data window using the source synchronous protocol. A pulse generator generates a pulse from the at least integrating strobe. An integrating receiver integrates the data over an integration window defined by the pulse. The integration window is within the data window.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 2, 2006
    Inventors: Roger Cheng, Navneet Dour, Scott Miller, David Freker, Harishankar Sridharan, Mahmood Alam
  • Publication number: 20060119381
    Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.
    Type: Application
    Filed: January 19, 2006
    Publication date: June 8, 2006
    Inventors: Navneet Dour, Roger Cheng
  • Publication number: 20050194991
    Abstract: Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 8, 2005
    Inventors: Navneet Dour, Roger Cheng
  • Publication number: 20040230576
    Abstract: Described is a system and method for applying transforms to multi-part files. A request is received to access a stream within a multi-part file. Upon receipt of the request, a list of transforms associated with the stream is identified. The list is also included within the multi-part file. The transforms specified in the list of transforms are performed on data before completing the request. If the request is a write, the transforms encode the data. If the request is a read, the transforms decode the data. The list of transforms is order dependent. The list of transforms includes a data structure having a first stream that includes a map that correlates the stream with a name for the list of transforms. A second stream that lists each of the transforms for the stream. A third stream for each of the transforms listed that identifies information associated with the transform.
    Type: Application
    Filed: May 17, 2003
    Publication date: November 18, 2004
    Applicant: Microsoft Corporation
    Inventors: Michael J. Hillberg, Roger Cheng, David B. Ornstein, Jason M. Cahill