Abstract: A power supply includes a PFC (power factor correction) converter that has an input and an output. The PFC converter input is coupled to an input of the power supply. The power supply also includes a resonant mode converter that has an input and an output. The resonant mode converter input is coupled to the PFC converter output and the resonant mode output is coupled to an output of the power supply. A control unit is also included in the power supply and is coupled to receive a feedback signal that is representative of the output of the power supply. The control unit is coupled to provide control signals coupled to control switches of the resonant mode converter at a controlled switching frequency to control the output of the power supply. The control unit is further coupled to provide a PFC control signal coupled to control a switch of the PFC converter at a switching frequency that is harmonically related to the controlled switching frequency.

Abstract: In a PFC (power factor correction) control unit for controlling a PFC converter, a transconductance amplifier is coupled to receive a feedback signal representative of an output voltage of the PFC converter. The transconductance amplifier is coupled to generate an output error signal in response to the feedback signal. A PWM (pulse width modulated) converter is coupled to receive the output error signal, the PWM converter is coupled to generate a PWM signal in response to the output error signal. A chopper is coupled to receive the PWM signal. The chopper is coupled to switch a current representative of an input current of the PFC converter in response to the PWM signal. A filter is coupled to receive the switched current representative of the input current of the PFC converter. The filter is coupled to generate a PFC converter control signal in response to the filtered switched current representative of the input current of the PFC converter.

Abstract: An apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM switching signal that controls a switch in a PFC converter. The control unit includes a PWM converter to produce a PWM signal responsive to an output voltage of the PFC converter. A switching circuit switches a current representing an input current of the PFC converter in response to the PWM signal. A circuit generates the control signal in response to the switched current. The control unit includes an amplifier that receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to generate the control signal. The offset unit provides the offset signal as an offset current for offsetting a current at an input of the amplifier.

Abstract: An apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM switching signal that controls a switch in a PFC converter. The control unit includes a PWM converter to produce a PWM signal responsive to an output voltage of the PFC converter. A switching circuit switches a current representing an input current of the PFC converter in response to the PWM signal. A circuit generates the control signal in response to the switched current. The control unit includes an amplifier that receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to generate the control signal. The offset unit provides the offset signal as an offset current for offsetting a current at an input of the amplifier.

Abstract: Power factor correction converter control offset apparatus and methods are disclosed. In one aspect, an apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM (Pulse Width Modulation) switching signal that controls a switch in a PFC (Power Factor Correction) converter. An offset unit is also included and is coupled to the control unit, to generate a variable offset signal to offset the control signal or a signal used by the control unit to generate the control signal.

Abstract: In a PFC (power factor correction) control unit for controlling a PFC converter, a transconductance amplifier is coupled to receive a feedback signal representative of an output voltage of the PFC converter. The transconductance amplifier is coupled to generate an output error signal in response to the feedback signal. A PWM (pulse width modulated) converter is coupled to receive the output error signal, the PWM converter is coupled to generate a PWM signal in response to the output error signal. A chopper is coupled to receive the PWM signal. The chopper is coupled to switch a current representative of an input current of the PFC converter in response to the PWM signal. A filter is coupled to receive the switched current representative of the input current of the PFC converter. The filter is coupled to generate a PFC converter control signal in response to the filtered switched current representative of the input current of the PFC converter.

Abstract: A power supply includes a PFC (power factor correction) converter that has an input and an output. The PFC converter input is coupled to an input of the power supply. The power supply also includes a resonant mode converter that has an input and an output. The resonant mode converter input is coupled to the PFC converter output and the resonant mode output is coupled to an output of the power supply. A control unit is also included in the power supply and is coupled to receive a feedback signal that is representative of the output of the power supply. The control unit is coupled to provide control signals coupled to control switches of the resonant mode converter at a controlled switching frequency to control the output of the power supply. The control unit is further coupled to provide a PFC control signal coupled to control a switch of the PFC converter at a switching frequency that is harmonically related to the controlled switching frequency.

Abstract: In a PFC (Power Factor Correction) converter control unit, a PWM (pulse width modulated) signal is produced by comparing a PFC converter output voltage error signal, produced by a transconductance amplifier, with a ramp signal, which may be from a control unit of a resonant mode converter in cascade with the PFC converter. Level shifting is used to match the amplitude ranges of the compared signals. A current, representing an input current of the PFC converter and produced by a current mirror, is switched by the PWM signal to a parallel resistance and capacitance to produce a smoothed voltage constituting a control signal for the PFC converter.

Abstract: A control unit controls cascaded PFC and LLC converters, the LLC converter having an input coupled to an output, of the PFC converter and providing an output voltage that decreases with increasing switching frequency. The control unit produces a sawtooth waveform with a linear ramp for controlling the LLC converter switching frequency, and hence its output voltage, in dependence upon a feedback signal. It also produces for the PFC converter a PWM signal with a frequency that is the same as or an integer fraction of the LLC converter switching frequency, by comparing two thresholds with the linear ramp in respective different cycles of the sawtooth waveform to turn on and off a switch of the PFC converter during these different cycles. Logic circuits prevent PFC converter switch transitions from occurring simultaneously with switching transitions of the LLC converter.

Abstract: Power factor correction converter control offset apparatus and methods are disclosed. In one aspect, an apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM (Pulse Width Modulation) switching signal that controls a switch in a PFC (Power Factor Correction) converter. An offset unit is also included and is coupled to the control unit, to generate a variable offset signal to offset the control signal or a signal used by the control unit to generate the control signal.

Abstract: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates can provide level-sensitive control of the latch.

Abstract: A control unit controls cascaded PFC and LLC converters, the LLC converter having an input coupled to an output, of the PFC converter and providing an output voltage that decreases with increasing switching frequency. The control unit produces a sawtooth waveform with a linear ramp for controlling the LLC converter switching frequency, and hence its output voltage, in dependence upon a feedback signal. It also produces for the PFC converter a PWM signal with a frequency that is the same as or an integer fraction of the LLC converter switching frequency, by comparing two thresholds with the linear ramp in respective different cycles of the sawtooth waveform to turn on and off a switch of the PFC converter during these different cycles. Logic circuits prevent PFC converter switch transitions from occurring simultaneously with switching transitions of the LLC converter.

Abstract: In a PFC (Power Factor Correction) converter control unit, a PWM (pulse width modulated) signal is produced by comparing a PFC converter output voltage error signal, produced by a transconductance amplifier, with a ramp signal, which may be from a control unit of a resonant mode converter in cascade with the PFC converter. Level shifting is used to match the amplitude ranges of the compared signals. A current, representing an input current of the PFC converter and produced by a current mirror, is switched by the PWM signal to a parallel resistance and capacitance to produce a smoothed voltage constituting a control signal for the PFC converter.

Abstract: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates can provide level-sensitive control of the latch.

Abstract: A power MOSFET, comprising main and current mirror MOSFETs, has a current sense resistance coupled between its mirror and source terminals and a monitoring circuit responsive to a first voltage dependent upon current through the current sense resistance. The circuit arrangement includes a circuit that determines a second voltage, different from the first voltage, of a terminal of the current mirror MOSFET, and a circuit arranged to determine current of the power MOSFET in dependence upon the first and second voltages. The second voltage can be the voltage at the drain terminal, or the voltage at the mirror terminal with switching of the current sense resistance or a current that it passes. It can alternatively be determined by a control circuit to be a desired fraction of the drain voltage.

Abstract: A power MOSFET, comprising main and current mirror MOSFETS, has a current sense resistance coupled between its mirror and source terminals and a monitoring circuit responsive to a first voltage dependent upon current through the current sense resistance. The circuit arrangement includes a circuit that determines a second voltage, different from the first voltage, of a terminal of the current mirror MOSFET, and a circuit arranged to determine current of the power MOSFET in dependence upon the first and second voltages. The second voltage can be the voltage at the drain terminal, or the voltage at the mirror terminal with switching of the current sense resistance or a current that it passes. It can alternatively be determined by a control circuit to be a desired fraction of the drain voltage.

Abstract: A class AB output stage of a CMOS amplifier has a level-shifting voltage follower constituted by a level-shifting transistor and a current source. A bias circuit replicates the level-shifting voltage follower in a feedback arrangement to produce a variable bias voltage for the current source of both the main and replica level-shifters. The arrangement serves to control the output voltage of the level-shifter such that it provides the amplifier with a relatively constant quiescent current of the output stage over variations of manufacturing process, supply voltage, and temperature. The level shifting function can be facilitated by a resistive on-state of a power-down transistor between the level-shifting and load transistors.

Abstract: A resistance ladder comprises a plurality of resistors in series, with taps for producing comparison voltage levels for an analog-to-digital converter (ADC), coupled at its ends to reference and common voltages via first and second adjustable resistances. The reference voltage is produced by an amplifier whose gain depends on a resistance ratio that is trimmed to determine a gain or full-scale range of the ADC. Offset trimming for the ADC is provided by making equal and opposite changes to the first and second adjustable resistances, so that the full-scale range is unchanged and the offset and gain adjustments are independent of one another.

Abstract: A class AB output stage of a CMOS amplifier has a level-shifting voltage follower constituted by a level-shifting transistor and a current source. A bias circuit replicates the level-shifting voltage follower in a feedback arrangement to produce a variable bias voltage for the current source of both the main and replica level-shifters. The arrangement serves to control the output voltage of the level-shifter such that it provides the amplifier with a relatively constant quiescent current of the output stage over variations of manufacturing process, supply voltage, and temperature. The level shifting function can be facilitated by a resistive on-state of a power-down transistor between the level-shifting and load transistors.

Abstract: An output pulse signal can be fabricated in an integrated circuit from an input signal. The output signal retains the desired pulse shape unaffected by jitter. A switched capacitor FIR filter is used to form the pulse shape, and then the clocking of the digital signals used to operate the pulse shaper is controlled to control the timing of different segments. The result is an output signal which has jitter but retains the desired pulse shape. Since a phase corrector which senses jitter can control the clocking, the output pulse shape is unaffected by jitter. The output pulse signal can be produced in an integrated circuit since switched capacitor pulse shapers are used, rather than a continuous time filter.