Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus includes an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

Abstract: A DRAM memory device having two sets of power buses is provided. Each set includes a first bus having a first potential and a second bus having a second potential, both of which are required to activate a row of memory within a bank of memory. A first row is activated while it is connected to the first set of buses. If it is detected that the activation of a second row connected to the first set of buses will cause a power bump when it is time to deactivate the first row, the first row is switched over to the second set of buses prior to the activation of the second row. The first row can be precharged with the voltages from the second set of buses and the second row can be activated with the voltages from the first set of buses. Thus, the first row can be precharged without being adversely effected by the power bump on the first set of buses which improves the pause performance of the DRAM.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: Testing of an integrated circuit having arrays of memory cells occurs by writing to all of the arrays at the same time. Normal writing occurs only to one array. Additional test data bus leads on the chip carry test data signals from selected arrays to comparison circuits. The outputs of the comparison circuits flow to the output circuits of the chip. This achieves writing test data to four times the number of arrays as in a normal write and reading test data from twice the number of arrays as in a normal read operation.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.