Abstract: Systems and methods for managing information technology (IT) resources determine the physical location of at least one managed element using a property of the at least one managed element, wherein the managed element is assigned a unique name within a container and the property specifies a value that indicates the physical location of the managed element within the container, further wherein the value is provided in a format that is standardized for the type of container.

Abstract: Systems, methods, and other embodiments associated with automatically detecting and characterizing a power topology are described. One example system includes a topology logic that identifies connections between PDUs and computers that receive power from the PDUs. The example system may include a data store that receives PDU/computer association data from the topology logic. A computer may communicate with a power providing PDU over a power line connecting the two devices. The computer and the power providing PDU may be configured with network interface devices (e.g., Ethernet switches) configured to communicate over the power line using, for example, EoP. The topology logic may discover a PDU/CE association by examining data transmitted over a network to which the computer and/or the PDU are connected.

Abstract: The present invention provides for repeatedly pulsing coolant through a first channel exposed to heat-generating computer components. The pulsing involves a relatively low baseline coolant flow rate with repeated excursions to a relatively high expulsion coolant flow rate.

Abstract: Systems, methods, and other embodiments associated with automatically detecting and characterizing a power topology are described. One example system includes a topology logic that identifies connections between PDUs and computers that receive power from the PDUs. The example system may include a data store that receives PDU/computer association data from the topology logic. A computer may communicate with a power providing PDU over a power line connecting the two devices. The computer and the power providing PDU may be configured with network interface devices (e.g., Ethernet switches) configured to communicate over the power line using, for example, EoP. The topology logic may discover a PDU/CE association by examining data transmitted over a network to which the computer and/or the PDU are connected.

Abstract: The present invention provides for repeatedly pulsing coolant through a first channel exposed to heat-generating computer components. The pulsing involves a relatively low baseline coolant flow rate with repeated excursions to a relatively high expulsion coolant flow rate.

Abstract: A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Abstract: A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Abstract: A method of adjusting power budgets of multiple servers within a data center comprises various actions. Such actions include, for example, organizing the multiple servers into hierarchical groups, dividing a total power budget among the hierarchical groups, and assigning power consumption levels to individual members of a particular hierarchical group such that the sum total of the assigned power consumption levels does not exceed the total power budget for the particular hierarchical group. The act of dividing is dynamic with respect to time.

Abstract: A system and method for connecting electrical components. More specifically, a method includes positioning a first set of electrical contacts of a first device opposite from a second set of electrical contacts of a second device, and activating a mechanism configured to rotate the first set of electrical contacts between an engaged position against the second set of electrical contacts and a disengaged position offset from the second set of electrical contacts.

Abstract: A method for adjusting power consumption during server operation is disclosed. The method comprises initializing the server to a system power performance state (SPP-state) that comprises a plurality of constituent power settings, determining whether power regulation is required while the server is operating at the current SPP-state, setting a flag if power regulation is required, and increasing at least one of the plurality of constituent power settings associated with the SPP-state if the flag has been set.

Abstract: Systems and methods for managing information technology (IT) resources determine the physical location of at least one managed element using a property of the at least one managed element, wherein the managed element is assigned a unique name within a container and the property specifies a value that indicates the physical location of the managed element within the container, further wherein the value is provided in a format that is standardized for the type of container.

Abstract: A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Abstract: A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Abstract: A method for adjusting power consumption during server operation is disclosed. The method comprises initializing the server to a system power performance state (SPP-state) that comprises a plurality of constituent power settings, determining whether power regulation is required while the server is operating at the current SPP-state, setting a flag if power regulation is required, and increasing at least one of the plurality of constituent power settings associated with the SPP-state if the flag has been set.

Abstract: A method of adjusting power budgets of multiple servers within a data center comprises various actions. Such actions include, for example, organizing the multiple servers into hierarchical groups, dividing a total power budget among the hierarchical groups, and assigning power consumption levels to individual members of a particular hierarchical group such that the sum total of the assigned power consumption levels does not exceed the total power budget for the particular hierarchical group. The act of dividing is dynamic with respect to time.

Abstract: In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt vector is received at the CPU. When a device connected to a lower speed bus sends an interrupt request, an interrupt queue device, connected to the CPU by a higher speed bus, intercepts the interrupt request, temporarily stores the corresponding interrupt vector and then responds to an interrupt acknowledge from the CPU by delivering the temporarily stored interrupt vector on the higher speed bus. In addition, the interrupt queue can deliver the temporarily stored interrupt vector to the CPU on a separate serial line.

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle.

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle.

Abstract: A computer system including the peripheral component interconnect (PCI) bus, including the LOCK# and STOP# signals and also having an extra sideband signal for supporting posted read transactions. The extra sideband signal, referred to as POST#, is used in conjunction with the LOCK# and STOP# signals defined in the PCI specification to implement the posted read. A posting target that determines that its read cycle is a long latency read, where the PCI bus should be released for non-exclusive accesses in the interim, asserts the STOP# and POST# signals to disconnect or retry the master and initiate a posted read. The master asserts the LOCK# signal in response to lock the posted target for the posted read, and then rearbitrates the PCI bus to other masters. Other masters may then access the PCI bus and perform non-exclusion access in the interim, while the posted target fetches the requested data.

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities.