Abstract: An expansion module for use in a computer system is disclosed. The expansion module holds a first card, which has a data processing unit and associated memory coupled together via a high speed internal local bus and an external coupler for an external peripheral device. An expansion coupler is also provided for coupling a second expansion card to the first card. The expansion module has a system connector for connecting the expansion module to a lower speed input-output bus of a computer system. The module can also accommodate additional SIMM modules as its associated memory. The module uses sidewalls or book covers made of a shielding material to provide electrical shielding and protection from external conditions. The expansion module improves the upgradeability and expandability of a data processing system.

Abstract: An enclosure for different subsystem variations of a data processing system has a box with front and rear regions separated by an interconnection carrier. The front is divided into standard-size bays for functional modules, while support modules slide into rear bays. A vertical central carrier contains electrical interconnections between the functional and support modules. An environmental module provides cooling air through the enclosure.

Abstract: A double-sided central electronics complex (CEC) is provided for increasing the logic card density in a logic cage or CEC. Specifically, two logic cages or sub-enclosures are integrated, sharing one backplane card so that logic elements may be plugged into the CEC from both sides. The CEC is formed by unitary sheet metal side plates, top and bottom cast or guides and a single double-sided backplane assembly.

Abstract: A double-sided backplane assembly is provided for increasing the logic element density in a logic cage or CEC. The backplane assembly is multi-layered with a backplane card centrally located between a stiffener and an EMC shield affixed to each side thereof. Connectors for connecting logic elements to the backplane card are provided on both sides of the backplane card, so that a logic cage having two sub-cages may be provided, the two sub-cages sharing the one backplane assembly.

Abstract: A data processing system is shown packaged in an enclosure wherein the system frame or chassis and a cable carrier are separately fabricated and thereafter merged to provide an enclosure with open ends and a central cable carrier that mounts connections for the system components. The system components are slideably received by the enclosure and are self docking as the electrical connections with the system power and signal lines are completed as the components arrive at the fully inserted, latched position. Keying means are also provided to require the user to install the components at both the correct location and with the correct orientation.

Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.