Abstract: The present invention relates to circuitry for processing an analog read signal, such as a signal produced by a magnetoresistive head, in a magnetic data storage system. The circuitry processes the analog signal before the signal reaches the detector which converts the analog signal into a digital signal representative of the data originally stored on the magnetic medium. In one embodiment, the invention comprises circuitry for equalizing the amplitudes of the positive and negative pulses in the analog read signal. In another embodiment, the invention comprises circuitry for reducing the baseline shift of the analog read signal. The invention may be used in magnetic data storage systems using any conventional data detection method.

Abstract: The present invention relates to circuitry for processing an analog read signal, such as a signal produced by a magnetoresistive head, in a magnetic data storage system. The circuitry processes the analog signal before the signal reaches the detector which converts the analog signal into a digital signal representative of the data originally stored on the magnetic medium. In one embodiment, the invention comprises circuitry for equalizing the amplitudes of the positive and negative pulses in the analog read signal. In another embodiment, the invention comprises circuitry for reducing the baseline shift of the analog read signal. The invention may be used in magnetic data storage systems using any conventional data detection method.

Abstract: The magnetic recording system of the present invention relaxes/reduces the magnetic energy in a magnetic recording head at the end of a write operation. In one embodiment, the magnetic recording system (10) includes a magnetic recording media (18), a recording head (14), and a biasing pattern (64) stored along a portion of the media (18). The biasing pattern (64) provides a biasing effect on the head (14) that provides controlled reduction of the magnetic energy domains in the head (14).

Abstract: Synchronous or coherent error appearing as one or more FM sidebands in the high frequency pulse signal of an incremental position encoding digital tachometer or the like and in an error signal having a magnitude representing the difference in velocity between that indicated by the high frequency signal and a desired velocity is suppressed in the error signal by a coherent error correction signal of varying magnitude which is combined with the error signal, is generated as a function of mechanical angular position and is identical from cycle to each cycle of the tachometer for the same mechanical angular position.

Abstract: A peak detector circuit has a first stage and a second stage. The first stage has a short time constant so that the level of the peaks are detected with a high bandwidth. A second stage follows the peaks detected in the first stage. The capacitor in the second stage is rapidly discharged when a new peak is detected by the first stage.