Abstract: Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

Abstract: A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.

Abstract: A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices.

Abstract: A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, while each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal.

Abstract: A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving.

Abstract: A system and method for managing the flow of data transfer requests from requesting devices to associated data transfer interconnection circuitry in a data processing system. Data transfers are initiated with data transfer requests that identify a data input queue and data output queue for which the data is to be transferred. The data transfer requests are issued from one or more requesting devices in the system. The data transfer requests are queued at a first queuing level. Within the first queuing level, data transfer requests identifying like data input queues are queued together, yet separate from data transfer requests identifying a different data input queue. Each of the data transfer requests from each of the queues in the first queuing level are transferred to a second queuing level to be queued according to the data output queue identified in the data transfer request. Each queue in the second queuing level stored only those data transfer requests identifying like data output queues.

Abstract: A new distributed control mechanism for managing bi-directional interfaces of symmetrical multiprocessor systems in such a manner as to minimize the latency to storage, yet fairly distribute the use of the interfaces amongst the various components. This bi-directional interface can be designed to perform with differing characteristics depending upon the direction of information flow. These characteristics are implemented into the control logic of the source and destination components interconnected by the bi-directional interface, thus yielding two interface behaviors using only one interface. Each component is able to track the state of the interface by using only its own request state in conjunction with the detected request state of the opposing component, when both units are operating under the joint control algorithm present in the control logic of the source and destination component.

Abstract: An improved memory request storage and allocation system using parallel queues to retain different categories of memory requests until they can be acted on by the main memory. Memory requests in the parallel queues are allowed to access the main memory according to a queue priority scheme. The queue priority scheme is based on an adjustable ratio, which determines the rate at which memory requests from one queue are allowed to access the main memory versus memory requests from other queues. Registers for bypassing the adjustable ratio eliminate delays by prohibiting the queue priority circuitry from attempting to retrieve a non-existent memory request from a queue. Conflict detection circuitry maintains proper instruction order in the parallel queue architecture by ensuring that subsequent memory requests, which have the same address as a memory request already in the queue, are placed in the same queue in the order that they were entered into the queue.