Abstract: Parts used in a construction project are fitted with a beacon that stores a unique part number identifier. The beacon includes a sensor that senses a current geographic location of the part on which it is installed. And asset locator correlates the geographic location of the part, to a location on a site plan drawing and generates a visual display indicating the location of the part, on the site plan drawing. The asset locator also filters shop drawings to identify a location, in each drawing, where the part is to be used in the construction project.

Abstract: Parts used in a construction project are fitted with a beacon that stores a unique part number identifier. The beacon includes a sensor that senses a current geographic location of the part on which it is installed. And asset locator correlates the geographic location of the part, to a location on a site plan drawing and generates a visual display indicating the location of the part, on the site plan drawing. The asset locator also filters shop drawings to identify a location, in each drawing, where the part is to be used in the construction project.

Abstract: A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Abstract: A method and apparatus for a unitary battery and charging circuit. Also, having a power conversion system includes a variable charging source and an energy storage device. The power conversion circuit also includes a charging circuit coupled to the variable charging source and the energy storage device, the energy storage device being charged by the variable charging source. Further, the circuit includes an energy storage device isolation circuit configured to isolate the energy storage device from discharging when power from the variable charging source is below a predetermined threshold. Further still, the conversion circuit includes a restart circuit configured to restart the charging circuit by utilizing power from the energy storage device when charging power has dropped below a predetermined level.

Abstract: A method and apparatus for a unitary battery and charging circuit that includes a first substrate having integrated-circuit battery-charging circuitry thereon, and a cathode material, an anode material, and an electrolyte layer separating the cathode material from the anode material deposited on the substrate to form a battery, wherein the charging circuit is connected to the battery and encapsulated to form a surface-mount unitary package. Also, a power conversion system includes a variable charging source and an energy storage device. The power conversion circuit also includes a charging circuit coupled to the variable charging source and the energy storage device, the energy storage device being charged by the variable charging source. Further, the circuit includes an energy storage device isolation circuit configured to isolate the energy storage device from discharging when power from the variable charging source is below a predetermined threshold.

Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: An apparatus having a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first phase control signal in response to a phase difference between a first input clock signal and a first output clock signal. The second circuit may be configured to generate a second phase control signal in response to a phase adjust signal. The third circuit may be configured to generate the first output clock signal by delaying the first input clock signal in response to a delay control signal. The delay control signal may be generated by summing the first and the second phase control signals.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first phase control signal in response to a phase difference between an input clock signal and an output clock signal. The second circuit may be configured to generate a second phase control signal in response to a phase adjust signal. The third circuit may be configured to generate the output clock signal in response to a phase adjustment of the input clock signal. The phase adjustment may be generated in response to a sum of the first and second phase control signals.

Abstract: A delay-locked loop circuit is provided which includes a delay-locked loop, a delay element and a multiplexer. The delay-locked loop has a reference clock input, a feedback clock input and a clock output. The delay element has a delay input which is coupled to the clock output and a delay output. The multiplexer has a first multiplexer input which is coupled to the clock output, a second multiplexer input which is coupled to the delay output and a multiplexer output which is coupled to the feedback input.

Abstract: An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control terminal. A pad pull-down transistor is coupled in series between the second voltage supply terminal and the pad terminal and has a pull-down control terminal. A voltage protection transistor is coupled between the pad terminal and the pad pull-down transistor. The voltage protection transistor has a control terminal and a capacitance between the control terminal and the pad terminal. A resistor is coupled in series between the control terminal of the voltage protection transistor and the third voltage supply terminal and forms a resistor-capacitor (RC) circuit with the capacitance.

Abstract: Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

Abstract: Thermally isolated circuit formed on a semiconductor on insulator structure includes a semiconductor surrounded by a semiconductor outer portion with an insulator therebetween. A cavity formed in the underlying semiconductor substrate opposite to the island provides thermal isolation.

Abstract: An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.

Abstract: An isolation structure as well as a method for using and fabricating an isolation structure in an active layer deposited on a substrate the method of fabrication including the steps of forming a buried oxide layer in the active layer adjacent the substrate, forming an isolation trench in the active layer by etching at least up to and optionally into the substrate, forming a dielectric isolation layer on the exposed surfaces of the trench, removing the dielectric isolation layer from the bottom of the trench, and forming an isolation structure by epitaxially growing monocrystalline silicon in the trench.