Patents by Inventor Roger M. Jeffery

Roger M. Jeffery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6459633
    Abstract: An integrated circuit has a plurality of buried metal fuses and an apparatus for selectively controlling the plurality of buried metal fuses. Each buried metal fuse has an output state. A plurality of latches each correspond to a respective one of the plurality of buried metal fuses. An encoding fuse has a first state and a second state. A plurality of gates, consists of either a plurality of XOR gates or a plurality of XNOR gates. Each gate has a first input coupled to the output of a respective one of the plurality of buried metal fuses and a second input coupled to the encoding fuse. Each gate has an output coupled to a respective one of the plurality of latches. Each of the plurality of latches has an output state that is the same as the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the first state.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 1, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Roger M. Jeffery, Peter T. Liu
  • Publication number: 20020054524
    Abstract: An integrated circuit has a plurality of buried metal fuses and an apparatus for selectively controlling the plurality of buried metal fuses. Each buried metal fuse has an output state. A plurality of latches each correspond to a respective one of the plurality of buried metal fuses. An encoding fuse has a first state and a second state. A plurality of gates, consists of either a plurality of XOR gates or a plurality of XNOR gates. Each gate has a first input coupled to the output of a respective one of the plurality of buried metal fuses and a second input coupled to the encoding fuse. Each gate has an output coupled to a respective one of the plurality of latches. Each of the plurality of latches has an output state that is the same as the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the first state.
    Type: Application
    Filed: December 20, 2001
    Publication date: May 9, 2002
    Inventors: Roger M. Jeffery, Peter T. Liu
  • Patent number: 6370074
    Abstract: An integrated circuit has a plurality of buried metal fuses and an apparatus for selectively controlling the plurality of buried metal fuses. Each buried metal fuse has an output state. A plurality of latches each correspond to a respective one of the plurality of buried metal fuses. An encoding fuse has a first state and a second state. A plurality of gates, consists of either a plurality of XOR gates or a plurality of XNOR gates. Each gate has a first input coupled to the output of a respective one of the plurality of buried metal fuses and a second input coupled to the encoding fuse. Each gate has an output coupled to a respective one of the plurality of latches. Each of the plurality of latches has an output state that is the same as the state of the respective one of the plurality of buried metal fuses to which that latch is coupled, when the encoding fuse is in the first state.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: April 9, 2002
    Assignee: Agere Systems Guardian Corp
    Inventors: Roger M. Jeffery, Peter T. Liu