Abstract: Under one aspect of the invention, the invention includes a multilayered substrate. The substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip. The substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip. The substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.

Abstract: A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode.