Patents by Inventor Roger T. Howe

Roger T. Howe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140049135
    Abstract: A thermionic energy converter is provided that includes an anode, a cathode, where the anode is disposed opposite the cathode, and a suspension, where a first end of the suspension is connected to the cathode and a second end of the suspension is connected to the anode, where the suspension moveably supports the cathode above the anode to form a variable gap between the anode and the cathode, where the variable gap is capable of enabling a variable thermionic current between the anode and the cathode, where the thermionic converter is capable of an AC power output.
    Type: Application
    Filed: July 17, 2013
    Publication date: February 20, 2014
    Inventors: Igor Bargatin, Roger T. Howe
  • Patent number: 8633573
    Abstract: Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e.g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: January 21, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jinendra Raja Jain, Roger T. Howe
  • Patent number: 8427251
    Abstract: Disclosed is an oscillator that relies on redundancy of similar resonators integrated on chip in order to fulfill the requirement of one single quartz resonator. The immediate benefit of that approach compared to quartz technology is the monolithic integration of the reference signal function, implying smaller devices as well as cost and power savings.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: April 23, 2013
    Assignee: The Regents of the University of California
    Inventors: Emmanuel P. Quevy, Roger T. Howe
  • Patent number: 8329559
    Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: December 11, 2012
    Assignee: The Regents of the University of California
    Inventors: Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King, Roger T. Howe
  • Patent number: 8313970
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 20, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 8288835
    Abstract: Microshells including a perforated pre-sealing layer and an integrated getter layer are provided. The integrated getter layer may be disposed between other layers of a perforated pre-sealing layer. The perforated pre-sealing layer may include at least one perforation, and a sealing layer may be provided on the pre-sealing layer to close the perforation.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 16, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 8273594
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 25, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Publication number: 20120229220
    Abstract: Disclosed is an oscillator that relies on redundancy of similar resonators integrated on chip in order to fulfill the requirement of one single quartz resonator. The immediate benefit of that approach compared to quartz technology is the monolithic integration of the reference signal function, implying smaller devices as well as cost and power savings.
    Type: Application
    Filed: March 26, 2007
    Publication date: September 13, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Emmanuel P. Quevy, Roger T. Howe
  • Publication number: 20120171798
    Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
    Type: Application
    Filed: April 19, 2007
    Publication date: July 5, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King, Roger T. Howe
  • Patent number: 7956517
    Abstract: A MEMS structure having a temperature-compensated resonator member is described. The MEMS structure comprises an asymmetric stress inverter member coupled with a substrate. A resonator member is housed in the asymmetric stress inverter member and is suspended above the substrate. The asymmetric stress inverter member is used to alter the thermal coefficient of frequency of the resonator member by inducing a stress on the resonator member in response to a change in temperature.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 7, 2011
    Assignee: Silicon Laboratories
    Inventors: Mehrnaz Motiee, Roger T. Howe, Emmanuel P. Quevy, David H. Bernstein
  • Publication number: 20110121412
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Publication number: 20110121416
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Publication number: 20110121415
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Patent number: 7923790
    Abstract: Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: April 12, 2011
    Assignee: Silicon Laboratories Inc.
    Inventors: Emmanuel P. Quevy, Pezhman Monadgemi, Roger T. Howe
  • Publication number: 20110068422
    Abstract: A MEMS coupler and a method to form a MEMS structure having such a coupler are described. In an embodiment, a MEMS structure comprises a member and a substrate. A coupler extends through a portion of the member and connects the member with the substrate. The member is comprised of a first material and the coupler is comprised of a second material. In one embodiment, the first and second materials are substantially the same. In one embodiment, the second material is conductive and is different than the first material. In another embodiment, a method for fabricating a MEMS structure comprises first forming a member above a substrate. A coupler comprised of a conductive material is then formed to connect the member with the substrate.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 24, 2011
    Inventors: Emmanuel P. Quevy, Roger T. Howe
  • Publication number: 20100327874
    Abstract: According to one aspect, the disclosure is directed to an example embodiment in which a circuit-based arrangement includes a circuit-based substrate securing a channel, with an effective width that is not limited by the Debye screening length, along a surface of the substrate. A pair of reservoirs are included in or on the substrate and configured for containing and presenting a sample having bio-molecules for delivery in the channel. A pair of electrodes electrically couple a charge in the sample to enhance ionic current flow therein (e.g., to overcome the electrolyte screening), and a sense electrode is located along the channel for sensing a characteristic of the biological sample by using the electrostatic interaction between the enhanced ionic current flow of the sample and the sense electrode. Actual detection occurs by using a charge-signal processing circuit to process the sensed charge signal and, therefrom, provide an output indicative of a signature for the bio-molecules delivered in the channel.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Yang Liu, Robert W. Dutton, Roger T. Howe
  • Patent number: 7858422
    Abstract: A MEMS coupler and a method to form a MEMS structure having such a coupler are described. In an embodiment, a MEMS structure comprises a member and a substrate. A coupler extends through a portion of the member and connects the member with the substrate. The member is comprised of a first material and the coupler is comprised of a second material. In one embodiment, the first and second materials are substantially the same. In one embodiment, the second material is conductive and is different than the first material. In another embodiment, a method for fabricating a MEMS structure comprises first forming a member above a substrate. A coupler comprised of a conductive material is then formed to connect the member with the substrate.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: December 28, 2010
    Assignee: Silicon Labs SC, Inc.
    Inventors: Emmanuel P. Quevy, Roger T. Howe
  • Publication number: 20100207254
    Abstract: Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e.g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material.
    Type: Application
    Filed: February 16, 2010
    Publication date: August 19, 2010
    Inventors: Jinendra Raja Jain, Roger T. Howe
  • Patent number: 7736929
    Abstract: Low temperature, multi-layered microshells for encapsulation of devices such as MEMS and microelectronics. The microshells may include a perforated pre-sealing layer, below which a sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The pre-sealing layer includes a large surface area getter layer to remove contaminants from the space ultimately enclosed by the microshell to improve the pressure control and cleanliness of the microshell.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 15, 2010
    Assignee: Silicon Clocks, Inc.
    Inventors: Pezhman Monadgemi, Emmanuel P. Quevy, Roger T. Howe
  • Patent number: 7659150
    Abstract: Microshells for encapsulation of devices such as MEMS and microelectronics. In an embodiment, the microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation as a function of the dimension of the perforation to form cavities having different vacuum levels on the same substrate.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: February 9, 2010
    Assignee: Silicon Clocks, Inc.
    Inventors: Pezhman Monadgemi, Roger T. Howe, Emmanuel P. Quevy