Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by different methods such as ion implantation, annealing and diffusion.

Abstract: A method of fabricating an interconnect of a capacitor. A substrate having a capacitor is provided. The capacitor comprises a bottom electrode electrically connected to the substrate, a dielectric layer and a top electrode thereon. A spin-on dielectric layer is formed on the substrate and the capacitor. The spin-on dielectric layer on the substrate is thicker than that on the top electrode. The spin-on dielectric layer is etched back until the top electrode is exposed. A patterned metal layer is formed on the spin-on dielectric layer and the top electrode with a bottom surface in directly contact with a top surface of the top electrode.

Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle.

Abstract: A method of fabricating an interconnect of a capacitor. A substrate having a capacitor is provided. The capacitor comprises a bottom electrode electrically connected to the substrate, a dielectric layer and a top electrode thereon. A spin-on dielectric layer is formed on the substrate and the capacitor. The spin-on dielectric layer on the substrate is thicker than that on the top electrode. The spin-on dielectric layer is etched back until the top electrode is exposed. A patterned metal layer is formed on the spin-on dielectric layer and the top electrode with a bottom surface in directly contact with a top surface of the top electrode.

Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved is disclosed. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by three different methods. In the first method, a copper seed layer is first deposited into a receptacle and an ion implantation process is carried out on the seed layer, which is followed by electroplating copper into the receptacle.

Abstract: A porous silicon layer is created by using wet etching to etch a polysilicon layer. In preferred embodiment, the polysilicon layer is treated by H.sub.3 PO.sub.4 solution at 60-165.degree. C. for about 3-200 minutes. The porous silicon layer is subsequently treated by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes to form a roughened polysilicon layer. The SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O. The volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20. The next step of the formation is the deposition of a dielectric film along the roughened surface of the micro-islands polysilicon layers. A conductive layer is deposited over the dielectric film. Next, photolithgraphy and etching process are used to etch the conductive layer, the dielectric film and the micro-islands polysilicon layer into a portion of the layer.

Abstract: A method and system for optimizing a steady-state performance of a process having multiple inputs and multiple output-responses is provided. The method and system provide a unified and systematic way of optimizing nominal, statistical and multi-criteria performance of the process. The process can be inter alia a semiconductor manufacturing process or a business process.